回复就给分，不给分是孙子，本人结帖率100%，protel99se中DRC错误问题

[aaaa456123]

回复就给分，不给分是孙子，本人结帖率100%，但是路过，顶这种回复恕小弟无法给分！
我用的是protel99，为什么一布内电层的时候就会这样？是不是过孔和内电层的分割线太近了，这个在99se里怎么设置？还望高手指教！


Processing Rule : Short-Circuit Constraint (Allowed=Not Allowed) (On the board ),(On the board )
Violation between Via (33313mil,15980mil) TopLayer to BottomLayer and
Polygon Track (33327mil,15997mil)(33327mil,16093mil) POWER
Violation between Via (33313mil,15980mil) TopLayer to BottomLayer and
Polygon Track (33222mil,15997mil)(33327mil,15997mil) POWER
Violation between Via (33207.803mil,15948mil) TopLayer to BottomLayer and
Polygon Track (33137mil,15949mil)(33393mil,15949mil) POWER
Violation between Via (32925mil,16440mil) TopLayer to BottomLayer and
Polygon Track (32733mil,16424mil)(33152mil,16424mil) POWER
Violation between Via (33113mil,16438mil) TopLayer to BottomLayer and
Polygon Track (32733mil,16424mil)(33152mil,16424mil) POWER
Violation between Via (33066mil,16397mil) TopLayer to BottomLayer and
Polygon Track (32951mil,16379mil)(33094mil,16379mil) POWER
Violation between Via (32737.33mil,16136.33mil) TopLayer to BottomLayer and
Polygon Track (32733mil,16017mil)(32733mil,16424mil) POWER
Violation between Via (33319mil,15416mil) TopLayer to BottomLayer and
Polygon Track (33083mil,15419mil)(34396mil,15419mil) POWER
Violation between Via (33313mil,15980mil) TopLayer to BottomLayer and
Polygon Track (33327mil,15997mil)(33327mil,16093mil) POWER
Violation between Via (33313mil,15980mil) TopLayer to BottomLayer and
Polygon Track (33208mil,15997mil)(33327mil,15997mil) POWER
Violation between Via (33207.803mil,15948mil) TopLayer to BottomLayer and
Polygon Track (33137mil,15949mil)(33393mil,15949mil) POWER
Violation between Via (33066mil,16397mil) TopLayer to BottomLayer and
Polygon Track (32951mil,16379mil)(33094mil,16379mil) POWER
Violation between Via (32925mil,16440mil) TopLayer to BottomLayer and
Polygon Track (32733mil,16424mil)(33152mil,16424mil) POWER
Violation between Via (33113mil,16438mil) TopLayer to BottomLayer and
Polygon Track (32733mil,16424mil)(33152mil,16424mil) POWER
Violation between Via (32737.33mil,16136.33mil) TopLayer to BottomLayer and
Polygon Track (32733mil,16017mil)(32733mil,16424mil) POWER
Violation between Via (33319mil,15416mil) TopLayer to BottomLayer and
Polygon Track (33083mil,15419mil)(34396mil,15419mil) POWER
Rule Violations :16



还有个小问题就是，提示说孔太大了，最大100个mil，可是这个洞是网口的固定孔，不能改小，还望高手指点如何在99se里设置，谢谢！

Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (On the board )
Violation Pad W1-0(31183.197mil,14434mil) MultiLayer Actual Hole Size = 129.921mil
Violation Pad W1-0(30733.197mil,14434mil) MultiLayer Actual Hole Size = 129.921mil
Violation Pad P1-(32700mil,14380mil) MultiLayer Actual Hole Size = 110mil
Violation Pad P1-(31714mil,14380mil) MultiLayer Actual Hole Size = 110mil
Rule Violations :4

[aaaa456123]

[Quote=引用 1 楼 slek 的回复:]

不会，帮顶
[/Quote]谢谢

[dontium]

[dontium]

[dontium]

“回复就给分，不给分是孙子……”
又

“但是路过，顶这种回复恕xx无法给分……"

[woshi_ziyu]

短路故障

过孔和线之间的具体太小 增大Clearance 重新铺铜

[bsnow]

前面短路问题应该是你间距问题！ 后面孔大小问题。由于我机器上没99se了。
但是在Altium里面 是在 Manufacturing的Hole Size里面。我估计99se应该也在那里修改！

[nandou]

检测下自己的设计规则

[jidesanhaofei110]

像是短路了

[net_friends]

不知道 谢谢

[yinyinehnzuotong]

有可能是短路了

[baoyz]

第一个问题是铺铜和过孔短路，注意网络设置是否正确。
第二个问题是规则设置问题，可以在规则设置对话框里找到过孔的设置项，把其中过孔“孔径”一项参数从100mil改为200mil。孔盘尺寸相应扩大。

[baoyz]

design->rules弹出对话框
选manufacturing标签
选Power Plane Clearance选项
这个是控制电源层间距的。

我用的是99，不知道第二个问题具体在哪，可以找有“VIA”字样的选项看看。

[byeyear]

99se不允许内电层分割跨同网络过孔。
例如，你的内电层网络名VCC，
那么在这个内电层上的split plane分割线不能压到任何网络名为VCC的pad或via