关于FPGA的485接收数据USB发送数据

[lx2014822]

module usb(
sys_clk,sys_rst_n,RO,RE_DE,USB_txd
);
input sys_clk ;
input sys_rst_n ;
input RO ;
output wire RE_DE ;
output USB_txd;
/***************reg define****************/
reg rxd_din1 ; //uart rxd input ;
reg rxd_din2 ; //uart rxd input ;
reg rxd_negedge_sig_flag ;
wire rxd_negedge_sig ;
reg [WIDTH-1:0] buff ;
reg [WIDTH-1:0] txd ; //temp txd signal;
reg USB_txd ;
reg [SIZE-1:0] counter ;
parameter WIDTH = 8 ;
parameter SIZE = 16 ;
/*******************************************************************************************************
** Main Program
**
********************************************************************************************************/
assign RE_DE = 1'b0;
always @ (posedge sys_clk or negedge sys_rst_n) begin
if ( sys_rst_n ==1'b0 )
begin
rxd_din1 <= 1'b0;
rxd_din2 <= 1'b0;
end
else
begin
rxd_din1 <= RO ;
rxd_din2 <= rxd_din1;
end
end

assign rxd_negedge_sig = (~rxd_din2) &(rxd_din1);

always @ (posedge sys_clk or negedge sys_rst_n) begin
if ( sys_rst_n ==1'b0)
rxd_negedge_sig_flag <= 1'b0;
else
rxd_negedge_sig_flag <= rxd_negedge_sig;
end

always @ (posedge sys_clk or negedge sys_rst_n) begin
if ( sys_rst_n == 1'b0 )
counter <= 16'b0;
else if ( rxd_negedge_sig_flag == 1'b1 && counter > 57288 )
counter <= 16'b0;
else if ( counter <= 57288 )
counter <= counter + 16'b1;
else ;
end

always @(posedge sys_clk or negedge sys_rst_n) begin
if ( sys_rst_n == 1'b0 )
buff <= 8'b0;
else begin
case ( counter )
7812 : buff[0] <= rxd_din1 ;
13020 : buff[1] <= rxd_din1 ;
18228 : buff[2] <= rxd_din1 ;
23436 : buff[3] <= rxd_din1 ;
28644 : buff[4] <= rxd_din1 ;
33852 : buff[5] <= rxd_din1 ;
39060 : buff[6] <= rxd_din1 ;
44268 : buff[7] <= rxd_din1 ;
default : buff <= buff ;
endcase
end
end
always @(posedge sys_clk or negedge sys_rst_n)
begin
if ((counter > 0) && (counter <= 5208 )) //
txd = 1'b0 ;
else if ((counter > 5208) && (counter <= 10416)) //
txd = buff[0] ;
else if ((counter > 10416) && (counter <= 15624)) //
txd = buff[1] ;
else if ((counter > 15624) && (counter <= 20832)) //
txd = buff[2] ;
else if ((counter > 20832) && (counter <= 26040)) //
txd = buff[3] ;
else if ((counter > 26040) && (counter <= 31248)) //
txd = buff[4] ;
else if ((counter > 31248) && (counter <= 36456)) //
txd = buff[5] ;
else if ((counter > 36456) && (counter <= 41664)) //
txd = buff[6] ;
else if ((counter > 41664) && (counter <= 46872)) //
txd = buff[7] ;
else if ((counter > 46800) && (counter <= 52000)) //
txd = 1'b1 ;
else if ((counter > 52000) && (counter <= 57200)) //
txd = 1'b1 ;
else
txd = 1'b1 ;
end
always @(posedge sys_clk or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0)
USB_txd <= 1'b1;
else
USB_txd <= txd;

end
endmodule
这段程序实现用485接收数据并通过USB发送数据，可是会报错：Error (10200): Verilog HDL Conditional Statement error at usb.v(86): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct
Error (12153): Can't elaborate top-level user hierarchy
求大神指教！感激不甚!!!!

[qq_19242161]

always @ (posedge sys_clk or negedge sys_rst_n) begin
if ( sys_rst_n == 1'b0 )
counter <= 16'b0;
else if ( rxd_negedge_sig_flag == 1'b1 && counter > 57288 )
counter <= 16'b0;
else if ( counter <= 57288 )
counter <= counter + 16'b1;
else ;
end

这段程序错误了， 这很好看啊，仔细点都会
第二个错误是应该没有顶层实体，如果这个.v 文件是顶层就设为顶层，不过我猜这应该不是顶层文件。

[Falcon7x]

always @ (posedge sys_clk or negedge sys_rst_n) 这个也不对吧？

[DDRn++]

这个没错啊，怎么会说它有错呢