关于FPGA的一个程序

[嘟嘟lu嘟嘟]

1.自定义一个分频器
2.使用分频信号交替驱动4颗led点亮
3.当按键按下时，分频器分频系数成倍增加，led的闪烁速度也发生变化
4.当另一个按键按下一次，关闭led闪烁，再次按下该键时，开启led闪烁


有好心人可以帮下忙吗

[fly 100%]

直接去pudn下载去吧。 有很多

[Taibuzhuanye]

这么简单的东西，自己写写就好了！

[everdisk]

我就发一个分频的程序，其他的可以自己练习练习！ module clkdiv( clk,rst_n, fm ); input clk; input rst_n; output reg fm; reg[19:0]cnt; always@(posedge clk or negedge rst_n) if(!rst_n)cnt<=20'd0; else if(cnt<20'd999_999) cnt<=cnt+1'b1; else cnt<=20'd0 endmodule

[guolh]

自己写吧，顺便练练手

[chat1]

下面是刚写的一种方法，已测试过

module div_led(
	input clk, //100M 
	input rst_n,
	
	input key1,	//low active 
	input key2,
	
	output led1,	//高电平点亮
	output led2,
	output led3,
	output led4
);
reg key1_d;	//1 clock delayed key1 
reg key2_d; //1 clock delayed key2 
reg [31:0] counter; //div counter
reg counter_ena_neg; //div counter enable, low active
reg [7:0] counter_inc_val; //1 clock increase value
wire key1_down;
wire key2_down;

assign key1_down = key1_d && ~key1;//按键是否按下，取下降沿 
assign key2_down = key2_d && ~key2;

always @(posedge clk) begin	//按键延时1周期
	key1_d <= key1;
	key2_d <= key2;
end

always @(posedge clk or negedge rst_n)//是否启动计数器
if (~rst_n)
	counter_ena_neg <= 1'b0;
else if (key2_down)
	counter_ena_neg <= ~counter_ena_neg;


always @(posedge clk or negedge rst_n)//计数器增加速度
if (~rst_n)
	counter_inc_val <= 8'b10000;
else if (key1_down)
	counter_inc_val <= {counter_inc_val[6:0], counter_inc_val[7]};

always @(posedge clk or negedge rst_n)	//计数器
if (~rst_n)
	counter <= 0;
else if (~counter_ena_neg)
	counter <= counter + counter_inc_val;
	
assign led1 = counter[31:30] == 2'd0;	//使用分频值点亮led
assign led2 = counter[31:30] == 2'd1;
assign led3 = counter[31:30] == 2'd2;
assign led4 = counter[31:30] == 2'd3;

endmodule

[wuyanwen1]

三楼的分频写的不咋样啊