有哪位VHDL大神能帮忙解决一下

[qq_30647243]

这是一个三人抢答器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY qd IS
PORT (a2,a1,a0:IN STD_LOGIC;
b: IN STD_LOGIC;
SPEAKER: OUT STD_LOGIC;
Y3,Y2,Y1,Y0:OUT STD_LOGIC);
END qd;
ARCHITECTURE ab OF qd IS
SIGNAL f: STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL S:STD_LOGIC;
SIGNAL c:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
c<=a2&a1&a0;
PROCESS(c,b)
BEGIN
IF b='1' THEN f<="0000";
S<='0';
ELSIF b='0' THEN
IF a0'EVENT AND a0'LAST_VALUE='0'
THEN f<="0001";S<='1';
ELSIF a1'EVENT AND a1'LAST_VALUE='0'
THEN f<="0010";S<='1';
ELSIF a2'EVENT AND a2'LAST_VALUE='0'
THEN f<="0011";S<='1';
END IF;
END IF;
END PROCESS;
Y3<=f(3);Y2<=f(2);Y1<=f(1);Y0<=f(0);
SPEAKER<=S;
END ab;



Error (10001): Verilog HDL or VHDL error at qd.vhd(20): can't infer register for S because its behavior depends on the edges of multiple distinct clocks
Error (10001): Verilog HDL or VHDL error at qd.vhd(20): can't infer register for S because it does not hold its value outside the clock edge
Error (10001): Verilog HDL or VHDL error at qd.vhd(20): can't infer register for f[0] because its behavior depends on the edges of multiple distinct clocks
Error (10001): Verilog HDL or VHDL error at qd.vhd(20): can't infer register for f[0] because it does not hold its value outside the clock edge
Error (10001): Verilog HDL or VHDL error at qd.vhd(20): can't infer register for f[1] because its behavior depends on the edges of multiple distinct clocks
Error (10001): Verilog HDL or VHDL error at qd.vhd(20): can't infer register for f[1] because it does not hold its value outside the clock edge
Error (10001): Verilog HDL or VHDL error at qd.vhd(20): can't infer register for f[2] because its behavior depends on the edges of multiple distinct clocks
Error (10001): Verilog HDL or VHDL error at qd.vhd(20): can't infer register for f[2] because it does not hold its value outside the clock edge
Error (10001): Verilog HDL or VHDL error at qd.vhd(20): can't infer register for f[3] because its behavior depends on the edges of multiple distinct clocks
Error (10001): Verilog HDL or VHDL error at qd.vhd(20): can't infer register for f[3] because it does not hold its value outside the clock edge
Error (10001): Verilog HDL or VHDL error at qd.vhd(20): couldn't implement registers for assignments on this clock edge
Error (10001): Verilog HDL or VHDL error at qd.vhd(22): couldn't implement registers for assignments on this clock edge
Error (10001): Verilog HDL or VHDL error at qd.vhd(24): couldn't implement registers for assignments on this clock edge
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 14 errors, 1 warning
Error: Processing ended: Tue Sep 27 23:25:20 2016
Error: Elapsed time: 00:00:03
Error: Quartus II Full Compilation was unsuccessful. 14 errors, 1 warning

[qq_30647243]

这是最新的修改，还是不行。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY qd IS PORT (a2,a1,a0:IN STD_LOGIC; b: IN STD_LOGIC; SPEAKER: OUT STD_LOGIC; Y3,Y2,Y1,Y0:OUT STD_LOGIC); END qd; ARCHITECTURE ab OF qd IS SIGNAL f: STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL S:STD_LOGIC; BEGIN PRO1:PROCESS(a0,b) BEGIN IF b='1' THEN f<="0000"; S<='0'; ELSIF b='0' THEN IF rising_edge (a0) THEN f<="0001";S<='1'; END IF; END IF; END PROCESS; PRO2:PROCESS(a1,b) BEGIN IF b='1' THEN f<="0000"; S<='0'; ELSIF b='0' THEN IF rising_edge (a1) THEN f<="0010";S<='1'; END IF; END IF; END PROCESS; PRO3:PROCESS(a2,b) BEGIN IF b='1' THEN f<="0000"; S<='0'; ELSIF b='0' THEN IF rising_edge (a2) THEN f<="0011";S<='1'; END IF; END IF; END PROCESS; Y3<=f(3);Y2<=f(2);Y1<=f(1);Y0<=f(0); SPEAKER<=S; END ab; Error (10028): Can't resolve multiple constant drivers for net "f[3]" at qd.vhd(28) Error (10029): Constant driver at qd.vhd(38) Error: Can't elaborate top-level user hierarchy

[fly 100%]

好像是f声明的类型有问题，声明称寄存器类型试试