fpga错误求大神相助

[王石石石]

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity eda1 is
port(clk,rst:in std_logic;
din : buffer std_logic_vector(2 downto 0);
dout:out std_logic_vector(15 downto 0);
row:out std_logic_vector(15 downto 0);
hl:buffer std_logic_vector(3 downto 0));
end eda1;
architecture a of eda1 is

begin
A:process(hl)
begin
case hl is
when "0000"=> row<="1000000000000000";
when "0001"=> row<="0100000000000000";
when "0010"=> row<="0010000000000000";
when "0011"=> row<="0001000000000000";
when "0100"=> row<="0000100000000000";
when "0101"=> row<="0000010000000000";
when "0110"=> row<="0000001000000000";
when "0111"=> row<="0000000100000000";
when "1000"=> row<="0000000010000000";
when "1001"=> row<="0000000001000000";
when "1010"=> row<="0000000000100000";
when "1011"=> row<="0000000000010000";
when "1100"=> row<="0000000000001000";
when "1101"=> row<="0000000000000100";
when "1110"=> row<="0000000000000010";
when "1111"=> row<="0000000000000001";
when others=> row<="0000000000000000";
END case;
end process A ;

B:process(clk,rst,din)
begin
if rst='1' then dout<="0000000000000000";
hl<="0000" ;din<="000";
elsif clk'event and clk='1' then
if din>6 then din<="000";
else din<=din +1;
if hl>15 then hl<="0000" ;
else hl<=hl+1;
end if;
case din is
when "000"=>
case hl is
when "0000" =>dout<="1000000000011111";
when "0001" =>dout<="0100001000010001";
when "0010" =>dout<="0010111110010001";
when "0011" =>dout<="0010001000010001";
when "0100" =>dout<="0001001000011111";
when "0101" =>dout<="1000001000010001";
when "0110" =>dout<="0100111111010001";
when "0111" =>dout<="0010100001010001";
when "1000" =>dout<="0001100001011111";
when "1001" =>dout<="0000100001010001";
when "1010" =>dout<="0001100001010001";
when "1011" =>dout<="0001111111010001";
when "1100" =>dout<="0010000000010001";
when "1101" =>dout<="0100000000100001";
when "1110" =>dout<="0100000001000111";
when "1111" =>dout<="0000000010000001";
when others=>dout<=null;
end case;
when "001"=>
case hl is
when "0000" =>dout<="0000000000000000";
when "0001" =>dout<="0000000100000000";
when "0010" =>dout<="0001111111111000";
when "0011" =>dout<="0000000100000000";
when "0100" =>dout<="0000000100000000";
when "0101" =>dout<="0000000100000000";
when "0110" =>dout<="0111111111111110";
when "0111" =>dout<="0100010010000010";
when "1000" =>dout<="0100001100000010";
when "1001" =>dout<="0100111111000010";
when "1010" =>dout<="0100000100000010";
when "1011" =>dout<="0100000100000010";
when "1100" =>dout<="0101111111111010";
when "1101" =>dout<="0100000100000010";
when "1110" =>dout<="0100000100000110";
when "1111" =>dout<="0000000000000011";
when others=>dout<=null;
end case;
when "010"=>
case hl is
when "0000" =>dout<="0000000000000000";
when "0001" =>dout<="0001111111111000";
when "0010" =>dout<="0001111111111000";
when "0011" =>dout<="0000000110000000";
when "0100" =>dout<="0000000110000000";
when "0101" =>dout<="0000000110000000";
when "0110" =>dout<="0000000110000000";
when "0111" =>dout<="0000000110000000";
when "1000" =>dout<="0000000110000000";
when "1001" =>dout<="0000000110000000";
when "1010" =>dout<="0000000110000000";
when "1011" =>dout<="0000000110000000";
when "1100" =>dout<="0000000110000000";
when "1101" =>dout<="0111111111111110";
when "1110" =>dout<="0111111111111110";
when "1111" =>dout<="0000000000000000";

when others=>dout<=null;
end case;
when "011"=>
case hl is
when "0000" =>dout<="0000010000000000";
when "0001" =>dout<="0000100000000000";
when "0010" =>dout<="0001000111111000";
when "0011" =>dout<="0011000100001000";
when "0100" =>dout<="1001000100001000";
when "0101" =>dout<="0001000111111000";
when "0110" =>dout<="0001000000100000";
when "0111" =>dout<="0111110000100000";
when "1000" =>dout<="0011100000100000";
when "1001" =>dout<="0101010000100000";
when "1010" =>dout<="1001001000100000";
when "1011" =>dout<="1001000011111000";
when "1100" =>dout<="1001000000100000";
when "1101" =>dout<="0001000000100000";
when "1110" =>dout<="0001011111111100";
when "1111" =>dout<="0000000000000000";
when others=>dout<=null;
end case;
when "100"=>
case hl is
when "0000" =>dout<="0010000100000100";
when "0001" =>dout<="0001000100001000";
when "0010" =>dout<="0000101001100000";
when "0011" =>dout<="0111111111111100";
when "0100" =>dout<="0100000000000010";
when "0101" =>dout<="0100111111100110";
when "0110" =>dout<="0000000000100000";
when "0111" =>dout<="0000001110000000";
when "1000" =>dout<="0000000010000000";
when "1001" =>dout<="0001111111111000";
when "1010" =>dout<="0000000001000000";
when "1011" =>dout<="0000000001000000";
when "1100" =>dout<="0000010001000000";
when "1101" =>dout<="0000001001000000";
when "1110" =>dout<="0000000110000000";
when "1111" =>dout<="0000000000000000";
when others=>dout<=null;
end case;
when "101"=>
case hl is
when "0000" =>dout<="0000000000000000";
when "0001" =>dout<="0111100011000000";
when "0010" =>dout<="0100100001100000";
when "0011" =>dout<="0101001111111100";
when "0100" =>dout<="0110010000000010";
when "0101" =>dout<="0110000011100100";
when "0110" =>dout<="0101000000000000";
when "0111" =>dout<="0110101111111000";
when "1000" =>dout<="0101000100000000";
when "1001" =>dout<="0100001010000000";
when "1010" =>dout<="0100010010000000";
when "1011" =>dout<="0100100010000000";
when "1100" =>dout<="0101000010001000";
when "1101" =>dout<="0100000001000110";
when "1110" =>dout<="0100000000111110";
when "1111" =>dout<="0000000000000000";
when others=>dout<=null;
end case;
when others=>null;
end case;end if;
end if;
end process;
end a;
这是程序错误
Warning (12019): Can't analyze file -- file /D???¡ì???t?D/eda1.vhd is missing
Error (12007): Top-level design entity "eda1" is undefined
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 1 error, 1 warning
Error: Peak virtual memory: 395 megabytes
Error: Processing ended: Tue Dec 13 16:06:09 2016
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:01
Error (293001): Quartus II Full Compilation was unsuccessful. 3 errors, 1 warning

[jiayou0909]

文件夹名和文件名不能有汉字

[Projectaker]

这是程序错误 Warning (12019): Can't analyze file -- file /D???¡ì???t?D/eda1.vhd is missing ------中文目录？ Error (12007): Top-level design entity "eda1" is undefined ------这里的名字必须和你的文件名字一致 Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 1 error, 1 warning Error: Peak virtual memory: 395 megabytes Error: Processing ended: Tue Dec 13 16:06:09 2016 Error: Elapsed time: 00:00:02 Error: Total CPU time (on all processors): 00:00:01 Error (293001): Quartus II Full Compilation was unsuccessful. 3 errors, 1 warning

[今天你芯动了吗]

首先我觉得上面的人说的有道理，文件位置不能有汉字，否则综合不了，你第一个错误D盘后面都是问号，应该是包含了汉字或者特殊字符。 其次就是第二个错误eda1无法识别，因为我是用Verilog所以为VHDL格式不是很了解，但个人感觉是你在写entity时每一行后面缺少或多出了分号，或者逗号或者什么的。我记得我在写verilog时候出现过类似的就是这个原因。但不是很确定，希望给楼主参考。