VHDL求助

[xchm007]

交织器VHDL程序 编译无错 但用modelism仿真时计数器模块出错 求大神帮忙看下是什么原因

# ** Error: E:/quartus/bishe/countern.vhd(19): Prefix (signal "q") for attribute "high" is not a type mark.
# ** Error: E:/quartus/bishe/countern.vhd(27): Prefix (signal "q") for attribute "high" is not a type mark.

--计数器模块
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
ENTITY countern IS
GENERIC(N:INTEGER:=16);
PORT(clr,ena,clk :in STD_LOGIC;
q: BUFFER INTEGER RANGE 0 TO N-1;
cout: OUT STD_LOGIC );
END countern;
ARCHITECTURE rtl OF countern IS BEGIN
PROCESS(clk,clr)
BEGIN
IF clr='1' THEN
q<=0;
ELSE
IF clk='1' AND clk'EVENT THEN
IF ena='1' THEN
IF q=q'high THEN
q<=0;
ELSE
q<=q+1;
END IF;
END IF;
END IF;
END IF;
IF q=q'high THEN
cout<='1';
ELSE
cout<='0';
END IF;
END PROCESS;
END rtl;