FPGA生成比特流出现以下错误

[weixin_40444038]

[DRC 23-20] Rule violation (LUTLP-1) Combinatorial Loop Alert - 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any net in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [net_nets <myHier/myNet>'. The cells in the loop are: pwm_OBUF_inst_i_10.

代码如下：
module twokhzz(
input wire clk,
input wire clr,
output reg pwm
);
parameter duty=87;
wire clk_390k;
reg[7:0] count;
reg[25:0]q;
always@(posedge clk or posedge clr) begin
if(clr==1)
q<=0;
else
q<=q+1;
end
assign clk_390k=q[7];
always@(clk_390k or clr)
if(clr) count<=0;
else if(count==194)
count<=0;
else
count<=count+1;
always@(*)
if(count<duty)
pwm<=1;
else
pwm<=0;
endmodule

[fly 100%]

这也写de太乱了 ，时钟逻辑里面就可以解决的， 这写的太容易产生竞争冒险