VHDL小错误:Error (10500): VHDL syntax error at main.vhd(30) near text "process"; e
Error (10500): VHDL syntax error at main.vhd(30) near text "process"; expecting "if"
代码:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity main is
port ( rst, en :in std_logic;
d_in :in std_logic_vector(2 downto 0);
din: in std_logic_vector(3 downto 0) ;
led0,led1,led2,led3,led4,led5 : buffer std_logic_vector(3 downto 0);
suc :out std_logic;
nsuc :out std_logic);
end main;
architecture behav of main is
begin
process(d_in)
begin
if rst='1' then
led0<="0000" ; led1<="0000" ;led2<="0000" ;led3<="0000" ;led4<="0000" ;led5<="0000" ;suc<='0';nsuc<='0';
elsif en='1' then
if d_in="000" then led0<=din; end if;
if d_in="001" then led1<=din; end if;
if d_in="010" then led2<=din; end if;
if d_in="011" then led3<=din; end if;
if d_in="100" then led4<=din; end if;
if d_in="101" then led5<=din; end if;
if d_in="110"then
if (led0 & led1 & led2 & led3 & led4 & led5 = "001000010100010001100110") then suc<='1';nsuc<='0';t<="00";else suc<='0';nsuc<='1';
end if;
end if;
end process;
end behav;