数字逻辑自动售卖机功能方针没问题，时序仿真没输出

[qq_41030699]

library ieee;
use ieee.std_logic_1164.all;
entity Sell is
port ( clk,rst:in std_logic;--clk
A,B: in std_logic;
Y,Z:out std_logic);
end Sell;

architecture struct of Sell is
type state is (S0,S1,S2,S3);
signal S:state;
begin
process (clk,rst)
begin
if rst='1' then
S<=S0;

elsif (clk'event and clk='1') then
case S is
when S0 =>
if (A='0' AND B='1') then
S<=S1;
Y<='0';Z<='0';
elsif (A='1' AND B='0') then
S<=S2;
Y<='0';Z<='0';
else
Y<='0';Z<='0';
end if;
when S1 =>
if (A='0' AND B='1') then
S<=S2;
Y<='0';Z<='0';
elsif (A='1' AND B='0') then
S<=S0;
Y<='1';Z<='0';
else
S<=S1;
end if;
when S2 =>
if (A='0' AND B='1') then
S<=S0;
Y<='1';Z<='0';
elsif (A='1' AND B='0') then
S<=S0;
Y<='1';Z<='1';
else
S<=S2;
end if;
when S3 =>
S <= S0;
when others =>
S<=S0;
end case;
end if;
end process;
end struct;