utopia Level1下载

weixin_39821526 2019-05-30 01:30:16

ATM Utopia接口规范标准。

eg.
UTOPIA, An ATM-PHY Interface Specification
Level 1, Version 2.01
March 21, 1994
(C) 1994 The ATM Forum. All Rights Reserved. Limited reproduction of this specification is authorized for
internal use only by companies that received it from The ATM Forum. External distribution i
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ATM Utopia接口规范标准。 eg. UTOPIA, An ATM-PHY Interface Specification Level 1, Version 2.01 March 21, 1994 (C) 1994 The ATM Forum. All Rights Reserved. Limited reproduction of this specification is authorized for internal use only by companies that received it from The ATM Forum. External distribution is prohibited. Other reproduction or external distribution is strictly prohibited.

This document describes a number of enhancements to the Universal Test & Operations PHY Interface for ATM (UTOPIA) data path interface [1]. This document assumes familiarity with the Level 1 Utopia document [1], which specifies the following : 1. an 8-bit wide data path, using an octet-level handshake, operating up to 25 MHz, with a single PHY device 2. an 8-bit wide data path, using an cell-level handshake, operating up to 25 MHz, with a single PHY device 3. a cell format and extra signals for a 16-bit wide data path for future use The Level 1 Specification was designed to deal with the following PHY layer interfaces : 1. 2. 3. 4. 5. 155.52 Mbps (SONET/OC-3c) 155.52 Mbps (8B/10B block coded) 100 Mbps (4B/5B TAXI) 44.1236 Mbps (DS-3) 51.84 Mbps (OC-1) We recommend use of this document in conjunction with the Level 1 Specification, since only updates and changes to it are described here.

* Cost effective, single chip, 8-port ATM IMA and UNI processor MT90220AL 208 Pin MQFP * Up to 4 IMA groups over 8 T1/E1 links can be implemented -40°C to +85°C * Supports MIXED mode; links not assigned to an * Provides Header Error Control (HEC) IMA group can be used in UNI mode verification and generation, error detection, * Versatile PCM Interface to most popular T1 or Filler cell filtering (IMA mode) and Idle/ E1 framers, reducing development time Unassigned cell filtering (UNI mode) * Supports Symmetrical and Asymmetrical * Provides statistics to support MIB Operation * Connects to popular asychronous SRAM * Supports both Common Transmit Clock (CTC) * Provides statistics on the number of HEC errors and Independent Transmit Clock (ITC) clocking modes * 8 bit Microprocessor Interface, compatible with Intel and Motorola * Supports T1 ISDN lines * Provides UTOPIA Level 2 MPHY Interface * 3.3V operation / 5V tolerant inputs (MT90220 device slaved to ATM device) * MQFP-208 pin * Complies with ITU G.804 recommendations for * JTAG Test support performing cell mapping into T1 and E1 transmission systems * Provides ATM framing using cell delineation according to the ITU I.432 cell delineation process

近期遇到了一个关于Utopia接口的问题。通常根据Utopia Level 2的标准，当Master在轮询PHY时，若对应的PHY有数据待发，则它要拉高其RX_CLAV。然后Master会将RX_ENB拉高，在下降沿选中该PHY，被选中的PHY会以一个RX_SOC脉冲开始数据的传输。请看从UL2 spec中摘录的描述。而当所有PHY都没有数据传送时，Master应该拉高其RX_EN

The Level 1 and Level 2 Utopia specifications describe the data path between a Physicallayer device and an ATM layer device, utilizing a 8-bit or 16-bit data path, catering fordata rates of up to

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