100进位 VHDL 测试通过
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity cuont is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (7 downto 0));
end cuont;
相关下载链接:
//download.csdn.net/download/u013102290/6690345?utm_source=bbsseo