帮忙看一下错误

[li610]

我是一个新手，刚编译一个乘法器程序，可总是有问题，不知怎么改，vhdl程序如下:
library IEEE;
use IEEE.Std_logic_1164.all;

ENTITY booth_multiplier IS
GENERIC(k POSITIVE := 7);
PORT(multiplicand, multiplier : IN BIT_VECTOR(k DOWNTO 0);
clock : IN BIT; product : INOUT BIT_VECTOR((2*k + 1) DOWNTO 0));
END booth_multiplier;

ARCHITECTURE structural OF booth_multiplier IS

SIGNAL mdreg, adderout, carries, augend, tcbuffout : BIT_VECTOR(k DOWNTO 0);
SIGNAL mrreg : BIT_VECTOR((k + 1) DOWNTO 0);
SIGNAL adder_ovfl : BIT;
SIGNAL comp ,clr_mr ,load_mr ,shift_mr ,clr_md ,load_md ,clr_pp ,load_pp ,shift_pp : BIT;
SIGNAL boostate : NATURAL RANGE 0 TO 2*(k + 1);

BEGIN

PROCESS
BEGIN
WAIT UNTIL (clock'EVENT AND clock = '1');


IF clr_md = '1' THEN
mdreg <= (OTHERS => '0');
ELSIF load_md = '1' THEN
mdreg <= multiplicand;
ELSE
mdreg <= mdreg;
END IF;


IF clr_mr = '1' THEN
mrreg <= (OTHERS => '0');
ELSIF load_mr = '1' THEN
mrreg((k + 1) DOWNTO 1) <= multiplier;
mrreg(0) <= '0';
ELSIF shift_mr = '1' THEN
mrreg <= mrreg SRL 1;
ELSE
mrreg <= mrreg;
END IF;


IF clr_pp = '1' THEN
product <= (OTHERS => '0');
ELSIF load_pp = '1' THEN
product((2*k + 1) DOWNTO (k + 1)) <= adderout;
product(k DOWNTO 0) <= product(k DOWNTO 0);
ELSIF shift_pp = '1' THEN
product <= product SRA 1;
ELSE
product <= product;
END IF;

END PROCESS;



augend <= product((2*k+1) DOWNTO (k+1));
addgen : FOR i IN adderout'RANGE
GENERATE
lsadder : IF i = 0 GENERATE
adderout(i) <= tcbuffout(i) XOR augend(i) XOR comp;
carries(i) <= (tcbuffout(i) AND augend(i)) OR
(tcbuffout(i) AND comp) OR
(comp AND augend(i));
END GENERATE;
otheradder : IF i /= 0 GENERATE
adderout(i) <= tcbuffout(i) XOR augend(i) XOR carries(i-1);
carries(i) <= (tcbuffout(i) AND augend(i)) OR
(tcbuffout(i) AND carries(i-1)) OR
(carries(i-1) AND augend(i));
END GENERATE;
END GENERATE;

adder_ovfl <= carries(k-1) XOR carries(k);



tcbuffout <= NOT mdreg WHEN (comp = '1') ELSE mdreg;



PROCESS BEGIN
WAIT UNTIL (clock'EVENT AND clock = '1');
IF boostate < 2*(k + 1) THEN boostate <= boostate + 1;
ELSE boostate <= 0;
END IF;
END PROCESS;



PROCESS(boostate)
BEGIN

comp <= '0';
clr_mr <= '0';
load_mr <= '0';
shift_mr <= '0';
clr_md <= '0';
load_md <= '0';
clr_pp <= '0';
load_pp <= '0';
shift_pp <= '0';
IF boostate = 0 THEN
load_mr <= '1';
load_md <= '1';
clr_pp <= '1';
ELSIF boostate MOD 2 = 0 THEN
shift_mr <= '1';
shift_pp <= '1';
ELSE --boostate = 1,3,5,7......
IF mrreg(0) = mrreg(1) THEN
NULL; --refresh pp
ELSE
load_pp <= '1';
END IF;
comp <= mrreg(1);
END IF;
END PROCESS;

END structural;
编译时总出现未知错误，为什么

[wangh503]

用什么编译的？

[li610]

max plus2

[色郎中]

向 benjaminweber 学习 呵呵

[benjaminweber]

至于吗？直接写一个乘号不行吗？干吗非自己写bit级别的。

一般用std_logic和std_logic_vector得比较好一些，当然你的也可以。

product干吗是inout，inout必须在顶层，而且必须以三态方式，否则无法综合。你的product显然不是三态门。

max plusII? 太古老了吧？
建议使用ModelSim + Quartus II.

wait语句不能综合。建议把clock放到testbench里面去。能综合的放一起，测试的代码放一起，你这么些，什么也不算呀。

Process要分开写。不要在一个process里给很多不相关的信号赋值。不相关的信号放在不同的process里面。

时钟触发的process不是这么写的，应该这样：
lock_write : PROCESS (PCLK, PRST)
BEGIN
IF PRST = '0' THEN
reg_data_write <= (OTHERS => '0');
reg_write_m <= '0';
ELSIF PCLK'EVENT AND PCLK = '1' THEN
IF wr_flag = '1' AND reg_write_m = '0' THEN
reg_data_write <= PWDATA(31 DOWNTO 0);
reg_write_m <= '1';
ELSE
reg_data_write <= PWDATA(31 DOWNTO 0);
reg_write_m <= '0';
END IF;
END IF;
END PROCESS lock_write;

PCLK是我的时钟。

好久没写了VHDL了，慢慢努力。

[wangguanyu2000]

好复杂