急问：VHDL在编译顶层电路图的错误问题？

[feiyun2002gl]

错误如下：Tri-state node must be driven by a TRI buffer, but is driven by primitive
ROM代码如下：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MODE_CONTROL IS
PORT(
FZ,FC:IN STD_LOGIC;
DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0); --IR
Q,T1,T2,T3,T4,CLR:IN STD_LOGIC;
LOAD,LDPC:OUT STD_LOGIC; --PC
LDAR:OUT STD_LOGIC; --AR
LDIR:OUT STD_LOGIC; --IR
LDR0,LDR1,LDR2,LDR3,R0_B,R1_B,R2_B,R3_B:OUT STD_LOGIC; --R0,R1,R2
S1,S0,ALU_B,LDAC,LDDR:OUT STD_LOGIC; --ALU
WR,CS:OUT STD_LOGIC; --范例中WR仅控制数据输出显示
SW_B,LED_B:OUT STD_LOGIC;
LDFR:OUT STD_LOGIC --LS74
);
END MODE_CONTROL;
ARCHITECTURE A OF MODE_CONTROL IS
SIGNAL YIMA:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL IN1,MOV,CMP,JN,INC,JMP,OUT1:STD_LOGIC;
SIGNAL RD0,RD1,RD2,RD3,RS0,RS1,RS2,RS3:STD_LOGIC;
SIGNAL LDRi,RS_B,RD_B:STD_LOGIC;
SIGNAL M:STD_LOGIC:='0';
BEGIN
P1:PROCESS(CLR,T4) --节拍电位设置
BEGIN
IF(CLR='0')THEN
M<='0';
ELSIF(T4'EVENT AND T4='0')THEN
M<=NOT M;
END IF;
END PROCESS P1;
P2:PROCESS(Q) --对操作码译码
BEGIN
CASE DIN(7 DOWNTO 4)IS
WHEN "1000"=>YIMA<="00000001";
WHEN "1001"=>YIMA<="00000010";
WHEN "1010"=>YIMA<="00000100";
WHEN "1011"=>YIMA<="00001000";
WHEN "1101"=>YIMA<="00010000";
WHEN "1110"=>YIMA<="00100000";
WHEN "1111"=>YIMA<="01000000";
WHEN OTHERS=>YIMA<="00000000";
END CASE;
--以下为控制信号的逻辑表达式
LDAC<=(CMP OR INC)AND T3 AND(NOT Q)AND(NOT M);
LDDR<=CMP AND T4 AND(NOT Q)AND(NOT M);
ALU_B<=NOT(INC AND T4 AND(NOT M));
LOAD<=NOT((JMP AND T4 AND(NOT M))OR(JN AND T4 AND (NOT M)AND(NOT FZ)));
LDPC<=(T1 AND (NOT Q)AND(NOT M))OR((MOV OR JN OR JMP)AND T3 AND (NOT Q)AND(NOT M))OR(JN AND T4 AND
(NOT Q)AND(NOT M)AND(NOT FZ))OR(JMP AND T4 AND(NOT Q)AND(NOT M));
LDIR<=T2 AND (NOT Q)AND(NOT M);
LDFR<=CMP AND T1 AND (NOT Q)AND M;
RS_B<=NOT((CMP OR OUT1)AND T3 AND(NOT M));
RD_B<=NOT((CMP AND T4 AND(NOT M))OR(INC AND T3 AND(NOT M)));
R0_B<=(RS_B OR DIN(3) OR DIN(2))AND(RD_B OR DIN(1)OR DIN(0));
R1_B<=(RS_B OR DIN(3) OR (NOT DIN(2)))AND(RD_B OR DIN(1)OR(NOT DIN(0)));
R2_B<=(RS_B OR (NOT DIN(3))OR DIN(2))AND(RD_B OR(NOT DIN(1))OR DIN(0));
R3_B<=(RS_B OR (NOT DIN(3))OR (NOT DIN(2)))AND(RD_B OR(NOT DIN(1))OR (NOT DIN(0)));
LDRi<=(IN1 AND T3 AND (NOT Q)AND(NOT M))OR(MOV AND T4 AND(NOT Q)AND(NOT M))
OR (INC AND T4 AND (NOT Q)AND (NOT M));
LDR0<=LDRi AND (NOT DIN(1))AND (NOT DIN(0));
LDR1<=LDRi AND(NOT DIN(1))AND DIN(0);
LDR2<=LDRi AND DIN(1) AND (NOT DIN(0));
LDR3<=LDRi AND DIN(1) AND DIN(0);
S1<=INC AND T4 AND (NOT M);
S0<=CMP AND T1 AND M;
CS<=NOT ((T2 AND (NOT M))OR (MOV AND T4 AND (NOT M))OR (JN AND T4 AND (NOT M)AND (NOT FZ))OR
(JMP AND T4 AND (NOT M)));
WR<=NOT (OUT1 AND T3 AND (NOT Q)AND (NOT M));
LDAR<=(T1 OR ((MOV OR JN OR JMP )AND T3))AND (NOT Q)AND (NOT M);
SW_B<=NOT (IN1 AND T3 AND (NOT M));
LED_B<=NOT (OUT1 AND T3 AND (NOT M));
END PROCESS P2;
-------译码信息转换成对应指令助记符
OUT1<=YIMA(6);
JMP<=YIMA(5);
INC<=YIMA(4);
JN<=YIMA(3);
CMP<=YIMA(2);
MOV<=YIMA(1);
IN1<=YIMA(0);
END A;
该ROM在编译生成图元时没错，但是在编译顶层电路图时则出错定位到该程序的：P2:PROCESS(Q) ；此处。

请高手帮我解决，本人不甚感激！

[feiyun2002gl]

高手快帮帮忙！

[xuanxing00]

如果Ｑ没有在进程中作为敏感信号使用就部要把它写在敏感信号表中

[ruiruio4]

程序看的晕，可是我看到P2:PROCESS(Q) 中
CASE DIN(7 DOWNTO 4)IS
WHEN "1000 "= >YIMA <= "00000001 ";
WHEN "1001 "= >YIMA <= "00000010 ";
WHEN "1010 "= >YIMA <= "00000100 ";
WHEN "1011 "= >YIMA <= "00001000 ";
WHEN "1101 "= >YIMA <= "00010000 ";
WHEN "1110 "= >YIMA <= "00100000 ";
WHEN "1111 "= >YIMA <= "01000000 ";
WHEN OTHERS= >YIMA <= "00000000 ";
END CASE;
怎么没有 WHEN "1100 " 的情况呀，而直接跨过到 WHEN "1101 "呢
呵呵，只是门外汉看乱子来着，不知道能不能对你有点帮助。

[dllklc]

貌似在process中并没有用到Q这个信号。。去掉试试吧