帮忙看一下,输入的信号被忽略了!
程序实现功能如下:
通过clk的脉冲,在recive=0时统计clk的跳变数,达到计时的目的,再把时间通过4个七段数码管显示出来。
程序代码如下:
library ieee;
use ieee.std_logic_1164.all;
entity device is
port(clk :in std_logic; --输入的时钟频率
recive :in std_logic; --计数开关
segs :out std_logic_vector(6 downto 0);--七段数码管的输出
segcs :out std_logic_vector(3 downto 0) --七段数码管的片选
);
end device;
architecture distance_device of device is
constant speed:integer:=278;--音速,在不同环境下有所不同
constant frequency:integer:=32768;--输入的时钟频率
signal temp: integer range 0 to 9;
signal count:integer; --计时的周期数
signal distance:integer; --距离,以分米为单位
begin
process(clk)
begin
segs<="0000000";
segcs<="0000";
if clk'event and clk='1' then
if recive='0' then
count<=count+1;
else
distance<=1000 * speed * count / frequency;--以毫米为单位
for i in 4 to 1 loop
temp<=distance / (i * 10);--高位
distance<=distance - (i * 10 * temp);
case temp is
when 0=> segs <= "1000000";
when 1=> segs <= "1111001";
when 2=> segs <= "0100100";
when 3=> segs <= "0110000";
when 4=> segs <= "0011001";
when 5=> segs <= "0010010";
when 6=> segs <= "0000011";
when 7=> segs <= "1111000";
when 8=> segs <= "0000000";
when 9=> segs <= "0011000";
end case;
for j in 4 to 1 loop
if(j=i) then
segcs(j)<='1';
else
segcs(j)<='0';
end if;
end loop;
end loop;
end if;
end if;
end process;
end distance_device;
每次编译提示如下:
warning:ignored unnecessary INPUT pin 'recive'
warning:ignored unnecessary INPUT pin 'clk'
波形仿真就无法继续下去了,请问这个是什么问题导致的?