Kevin_qing(Kevin)，交个朋友好吗？

lyzcom 2001-07-19 10:03:35

这几次多谢你的关心和帮助。其实我本来是在DOS编程的，而且也玩了几年的编程了。只是这几天才开始往VC下转。刚一开始，有很多东西都不习惯，也不明白，慢慢的就会好了。而且，我们这里近几天开始打假，网费也上涨，想买一本DX7SDK的光盘都买不到，上网下又划不来，只有问你了，非常谢谢，真的！我相信，只要几个月的时间，我就能马上顺应DX的。如果你愿意的话，我们交个朋友可以吗？我的QQ号码是：1310642

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本资源是ESXI6.7.0，于2019年12月我制作的一个集成intel e1000网卡的镜像包，本人已在自己的设备上稳定使用大半年，现在将资源分享给有需要的同学，注意是集成e1000网卡，其他网卡不保证

以前和大家分享过SIGMOD2009的论文，朋友们都很感兴趣，现手里有SIGMOD211的全部论文，再次和大家分享~ 一个包放不下，一共分成了3个包，包含百余篇论文，朋友们可以挑选自己感兴趣的部分下载，我尽量把文章目录写得明白一些。这是第二部分。 Nearest Keyword Search in XML Documents (Page 589) Yufei Tao (Chinese University of Hong Kong) Stavros Papadopoulos (Chinese University of Hong Kong) Cheng Sheng (Chinese University of Hong Kong) Kostas Stefanidis (Chinese University of Hong Kong) Efficient and Generic Evaluation of Ranked Queries (Page 601) Wen Jin (Independent Consultant) Jignesh M. Patel (University of Wisconsin - Madison) (Return to Top) Session 13: Stream and Complex Event Processing Changing Flights in Mid-Air: A Model for Safely Modifying Continuous Queries (Page 613) Kyumars Sheykh Esmaili (ETH Zurich) Tahmineh Sanamrad (ETH Zurich) Peter M. Fischer (ETH Zurich) Nesime Tatbul (ETH Zurich) How Soccer Players Would Do Stream Joins (Page 625) Jens Teubner (ETH Zurich) Rene Mueller (IBM Almaden Research Group) BE-Tree: An Index Structure to Efficiently Match Boolean Expressions Over High-Dimensional Discrete Space (Page 637) Mohammad Sadoghi (University of Toronto) Hans-Arno Jacobsen (University of Toronto) TI: An Efficient Indexing Mechanism for Real-Time Search on Tweets (Page 649) Chun Chen (Zhejiang University) Feng Li (National University of Singapore) Beng Chin Ooi (National University of Singapore) Sai Wu (National University of Singapore) (Return to Top) Session 14: Query Processing More Efficient Datalog Queries: Subsumptive Tabling Beats Magic Sets (Page 661) K. Tuncay Tekle (LogicBlox, Inc.) Yanhong A. Liu (State University of New York at Stony Brook) Entangled Queries: Enabling Declarative Data-Driven Coordination (Page 673) Nitin Gupta (Cornell University) Lucja Kot (Cornell University) Sudip Roy (Cornell University) Gabriel Bender (Cornell University) Johannes Gehrke (Cornell University) Christoph Koch (École Polytechnique Fédérale de Lausanne) Data Generation Using Declarative Constraints (Page 685) Arvind Arasu (Microsoft Research) Raghav

[JAVA工程师必会知识点之并发编程]1、现在几乎100%的公司面试都必须面试并发编程，尤其是互联网公司，对于并发编程的要求更高，并发编程能力已经成为职场敲门砖。2、现在已经是移动互联和大数据时代，对于应用程序的性能、处理能力、处理时效性要求更高了，传统的串行化编程无法充分利用现有的服务器性能。3、并发编程是几乎所有框架的底层基础，掌握好并发编程更有利于我们学习各种框架。想要让自己的程序执行、接口响应、批处理效率更高，必须使用并发编程。4、并发编程是中高级程序员的标配，是拿高薪的必备条件。【主讲讲师】尹洪亮Kevin：现任职某互联网公司首席架构师，负责系统架构、项目群管理、产品研发工作。10余年软件行业经验,具有数百个线上项目实战经验。擅长JAVA技术栈、高并发高可用伸缩式微服务架构、DevOps。主导研发的蜂巢微服务架构已经成功支撑数百个微服务稳定运行【推荐你学习这门课的理由：知识体系完整+丰富学习资料】1、本课程总计122课时，由五大体系组成，目的是让你一次性搞定并发编程。分别是并发编程基础、进阶、精通篇、Disruptor高并发框架、RateLimiter高并发访问限流吗，BAT员工也在学。2、课程附带附带3个项目源码，几百个课程示例，5个高清PDF课件。3、本课程0基础入门，从进程、线程、JVM开始讲起，每一个章节只专注于一个知识点，每个章节均有代码实例。【课程分为基础篇、进阶篇、高级篇】一、基础篇基础篇从进程与线程、内存、CPU时间片轮训讲起，包含线程的3种创建方法、可视化观察线程、join、sleep、yield、interrupt，Synchronized、重入锁、对象锁、类锁、wait、notify、线程上下文切换、守护线程、阻塞式安全队列等内容。二、进阶篇进阶篇课程涵盖volatied关键字、Actomic类、可见性、原子性、ThreadLocal、Unsafe底层、同步类容器、并发类容器、5种并发队列、COW容器、InheritableThreadLocal源码解析等内容。三、精通篇精通篇课程涵盖JUC下的核心工具类，CountDownLath、CyclicBarrier、Phaser、Semaphore、Exchanger、ReentrantLock、ReentrantReadWriteLock、StampedLock、LockSupport、AQS底层、悲观锁、乐观锁、自旋锁、公平锁、非公平锁、排它锁、共享锁、重入锁、线程池、CachedThreadPool、FixedThreadPool、ScheduledThreadPool、SingleThreadExecutor、自定义线程池、ThreadFactory、线程池切面编程、线程池动态管理等内容，高并发设计模式，Future模式、Master Worker模式、CompletionService、ForkJoin等课程中还包含Disruptor高并发无锁框架讲解：Disruptor支持每秒600万订单处理的恐怖能力。深入到底层原理和开发模式，让你又懂又会用。高并发访问限流讲解：涵盖木桶算法、令牌桶算法、Google RateLimiter限流开发、Apache JMeter压力测试实战。【学完后我将达到什么水平？】1、吊打一切并发编程相关的笔试题、面试题。2、重构自己并发编程的体系知识，不再谈并发色变。3、精准掌握JAVA各种并发工具类、方法、关键字的原理和使用。4、轻松上手写出更高效、更优雅的并发程序，在工作中能够提出更多的解决方案。【面向人群】1、总感觉并发编程很难、很复杂、不敢学习的人群。2、准备跳槽、找工作、拿高薪的程序员。3、希望提高自己的编程能力，开发出更高效、性能更强劲系统的人群。4、想要快速、系统化、精准掌握并发编程的人群。【课程知识体系图】

Springer - High performance Packet Switching Architectures(2007) List of Contributors ..............................................................................................xi 1 Architectures of Internet Switches and Routers ............................................ 1 Xin Li, Lotfi Mhamdi, Jing Liu, Konghong Pun, and Mounir Hamdi 1.1 Introduction ...............................................................................................2 1.2 Bufferless Crossbar Switches ................................................................... 3 1.2.1 Introduction to Switch Fabrics ....................................................... 3 1.2.2 Output-queued Switches ................................................................4 1.2.3 Input-queued Switches ..................................................................4 1.2.4 Scheduling Algorithms for VOQ Switches ................................... 5 1.2.5 Combined Input–Ouput-queued Switches ..................................... 9 1.3 Buffered Crossbar Switches .................................................................... 12 1.3.1 Buffered Crossbar Switches Overview......................................... 12 1.3.2 The VOQ/BCS Architecture ........................................................13 1.4 Multi-stage Switching ............................................................................. 19 1.4.1 Architecture Choice......................................................................19 1.4.2 The MSM Clos-network Architecture ......................................... 20 1.4.3 The Bufferless Clos-network Architecture ................................... 23 1.5 Optical Packet Switching ........................................................................27 1.5.1 Multi-rack Hybrid Opto-electronic Switch Architecture ............. 27 1.5.2 Optical Fabrics .............................................................................28 1.5.3 Reduced Rate Scheduling ............................................................30 1.5.4 Time Slot Assignment Approach ................................................. 30 1.5.5 DOUBLE Algorithm ...................................................................32 1.5.6 ADJUST Algorithm .....................................................................32 1.6 Conclusion ....... .......................................................................................34 2 Theoretical Performance of Input-queued Switches Using Lyapunov Methodology....................................................................... 39 Andrea Bianco, Paolo Giaccone, Emilio Leonardi, Marco Mellia, and Fabio Neri 2.1 Introduction .............................................................................................39 2.2 Theoretical Framework ...........................................................................41 v iii Contents 2.2.1 Description of the Queueing System ........................................... 41 2.2.2 Stability Definitions for a Queueing System ............................... 43 2.2.3 Lyapunov Methodology ..............................................................44 2.2.4 Lyapunov Methodology to Bound Queue Sizes and Delays ....... 47 2.2.5 Application to a Single Queue ..................................................... 48 2.2.6 Final Remarks ..............................................................................49 2.3 Performance of a Single Switch .............................................................. 50 2.3.1 Stability Region of Pure Input-queued Switches ......................... 51 2.3.2 Delay Bounds for Maximal Weight Matching ............................. 54 2.3.3 Stability Region of CIOQ with Speedup 2 ................................... 55 2.3.4 Scheduling Variable-size Packets................................................. 57 2.4 Networks of IQ Switches......................................................................... 58 2.4.1 Theoretical Performance...............................................................59 2.5 Conclusions .............................................................................................61 3 Adaptive Batched Scheduling for Packet Switching with Delays ............... 65 Kevin Ross and Nicholas Bambos 3.1 Introduction .............................................................................................65 3.2 Switching Modes with Delays: A General Model ................................... 66 3.3 Batch Scheduling Algorithms ................................................................. 69 3.3.1 Fixed Batch Policies .....................................................................70 3.3.2 Adaptive Batch Policies................................................................ 72 3.3.3 The Simple-batch Static Schedule ................................................ 73 3.4 An Interesting Application: Optical Networks ........................................ 74 3.5 Throughput Maximization via Adaptive Batch Schedules ...................... 76 3.6 Summary .................................................................................................78 4 Geometry of Packet Switching: Maximal Throughput Cone Scheduling Algorithms .................................................................................. 81 Kevin Ross and Nicholas Bambos 4.1 Introduction .............................................................................................81 4.2 Backlog Dynamics of Packet Switches.................................................... 84 4.3 Switch Throughput and Rate Stability ..................................................... 86 4.4 Cone Algorithms for Packet Scheduling.................................................. 88 4.4.1 Projective Cone Scheduling (PCS)............................................... 89 4.4.2 Relaxation, Generalizations, and Delayed PCS (D-PCS)............. 90 4.4.3 Argument Why PCS and D-PCS Maximize Throughput ............. 92 4.4.4 Quality of Service and Load Balancing........................................ 93 4.5 Complexity in Cone Schedules – Scalable PCS Algorithms ................... 95 4.5.1 Approximate PCS......................................................................... 95 4.5.2 Local PCS..................................................................................... 95 4.6 Final Remarks .........................................................................................98 5 Fabric on a Chip: A Memory-management Perspective ........................... 101 Itamar Elhanany, Vahid Tabatabaee, and Brad Matthews 5.1 Introduction ...........................................................................................101 5.1.1 Benefits of the Fabric-on-a-Chip Approach ............................... 102 5.2 Emulating an Output-queued Switch .................................................... 103 Contents ix 5.3 Packet Placement Algorithm ................................................................. 105 5.3.1 Switch Architecture ................................................................... 105 5.3.2 Memory-management Algorithm and Related Resourses .......... 106 5.3.3 Sufficiency Condition on the Number of Memories................... 109 5.4 Implementation Considerations ............................................................. 114 5.4.1 Logic Dataflow........................................................................... 114 5.4.2 FPGA Implementation Results ................................................... 119 5.5 Conclusions ........................................................................................... 120 6 Packet Switch with Internally Buffered Crossbars.................................... 121 Zhen Guo, Roberto Rojas-Cessa, and Nirwan Ansari 6.1 Introduction to Packet Switches.............................................................121 6.2 Crossbar-based Switches .......................................................................122 6.3 Internally Buffered Crossbars ................................................................ 124 6.4 Combined Input–Crosspoint Buffered (CICB) Crossbars ..................... 126 6.4.1 FIFO–CICO Switches ................................................................ 126 6.4.2 VOQ–CICB Switches ................................................................ 128 6.4.3 Separating Matching into Input and Output Arbitrations ........... 130 6.4.4 Weighted Arbitration Schemes................................................... 130 6.4.5 Arbitration Schemes based on Round-robin Selection .............. 135 6.5 CICB Switches with Internal Variable-length Packets .......................... 141 6.6 Output Emulation by CICB Switches ................................................... 141 6.7 Conclusions ........................................................................................... 144 7 Dual Scheduling Algorithm in a Generalized Switch: Asymptotic Optimality and Throughput Optimality................................. 147 Lijun Chen, Steven H. Low, and John C. Doyle 7.1 Introduction ...........................................................................................148 7.2 System Model .. .....................................................................................150 7.2.1 Queue Length Dynamics ........................................................... 151 7.2.2 Dual Scheduling Algorithm ....................................................... 152 7.3 Asymptotic Optimality and Fairness ..................................................... 153 7.3.1 An Ideal Reference System ....................................................... 153 7.3.2 Stochastic Stability .................................................................... 154 7.3.3 Asymptotic Optimality and Fairness .......................................... 155 7.4 Throughput-optimal Scheduling ...........................................................159 7.4.1 Throughput Optimality and Fairness ......................................... 159 7.4.2 Optimality Proof ........................................................................160 7.4.3 Flows with Exponentially Distributed Size ............................... 163 7.5 A New Scheduling Architecture ........................................................... 165 7.6 Conclusions ........................................................................................... 166 8 The Combined Input and Crosspoint Queued Switch............................... 169 Kenji Yoshigoe and Ken Christensen 8.1 Introduction ...........................................................................................169 8.2 History of the CICQ Switch .................................................................. 172 8.3 Performance of CICQ Cell Switching .................................................. 175 8.3.1 Traffic Models ........................................................................... 176 x Contents 8.3.2 Simulation Experiments .............................................................177 8.4 Performance of CICQ Packet Switching .............................................. 179 8.4.1 Traffic Models ........................................................................... 179 8.4.2 Simulation Experiments .............................................................179 8.5 Design of Fast Round-robin Arbiters .................................................... 181 8.5.1 Existing RR Arbiter Designs ..................................................... 182 8.5.2 A New Short-term Fair RR Arbiter – The Masked Priority Encoder (MPE) ...... .................................................................... 183 8.5.3 A New Fast Long-term Fair RR Arbiter – The Overlapped RR (ORR) Arbiter ............................................................................. 186 8.6 Future Directions – The CICQ with VCQ ............................................ 188 8.6.1 Design of Virtual Crosspoint Queueing (VCQ) ........................ 189 8.6.2 Evaluation of CICQ Cell Switch with VCQ .............................. 190 8.7 Summary ...............................................................................................192 9 Time–Space Label Switching Protocol (TSL-SP)....................................... 197 Anpeng Huang, Biswanath Mukherjee, Linzhen Xie, and Zhengbin Li 9.1 Introduction ...........................................................................................197 9.2 Time Label ............................................................................................ 198 9.3 Space Label ........................................................................................... 200 9.4 Time–Space Label Switching Protocol (TSL-SP) ................................. 201 9.5 Illustrative Results .................................................................................205 9.6 Summary ...............................................................................................209 10 Hybrid Open Hash Tables for Network Processors................................... 211 Dale Parson, Qing Ye, and Liang Cheng 10.1 Introduction ........................................................................................... 211 10.2 Conventional Hash Algorithms ............................................................. 213 10.2.1 Chained Hash Tables ................................................................ 214 10.2.2 Open Hash Tables ..................................................................... 215 10.3 Performance Degradation Problem ...................................................... 216 10.3.1 Improvements .......................................................................... 218 10.4 Hybrid Open Hash Tables .................................................................... 219 10.4.1 Basic Operations ...................................................................... 219 10.4.2 Basic Ideas ............................................................................... 219 10.4.3 Performance Evaluation ......................................................... 220 10.5 Hybrid Open Hash Table Enhancement ............................................... 222 10.5.1 Flaws of Hybrid Open Hash Table ........................................... 222 10.5.2 Dynamic Enhancement .............................................................223 10.5.3 Adaptative Enhancement .......................................................... 224 10.5.4 Timeout Enhancement .............................................................. 224 10.5.5 Performance Evaluation ......................................................... 224 10.6 Extended Discussions of Concurrency Issues ...................................... 225 10.6.1 Insertion ....................................................................................225 10.6.2 Clean-to-copy Phase Change .................................................... 226 10.6.2 Timestamps................................................................................227 10.7 Conclusion ....... ..................................................................................... 227 Index .................................... ............................................................................... 229

构造使用类C语言的脚本引擎(3)作者 :kevin_qing转贴请注明现在回到编译器上的构造上。编译分为4个步骤1.预处理在这里我只是替换掉源文件的字符/r->/n/0->0x20 (空格)并且在源文件最后加上/02.词法分析.词法分析主要是将输入流分割为一个个的单词，在这里我并未使用flex而是自己实现。(看到正则表达式就晕，更别说叫我写了,而且注视的正则也不好写，还不如自己做比

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