sequential execution和selection execution是什么啊？

changeking 2008-10-08 07:11:04
请问
sequential execution和selection execution是什么啊,有没有详细的解释?
明天考试，刚发现这些概念类的我完全不知道~~
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richard_2010 2008-10-08
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顺序执行： 一直执行下去。
选择执行：选择性的执行。
代码已经有了
懂了就结贴吧
gesanri 2008-10-08
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顺序执行：


int a=1;

a=a+1;

System.out.print(a);


选择执行：


if(a>1)

   a++;

else

   a--;
changeking 2008-10-08
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能不能再说具体一点?什么是顺序执行和选择执行,能不能举个例?谢谢了
抬头望远，低头沉思 2008-10-08
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sequential execution 顺序执行
selection execution 选择执行
是java基础的三种控制结构之一，还有一个循环
changeking 2008-10-08
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谢谢楼上的大哥，我开始懂了`
Programming.multicore.and.many-core.computing.systems.epub
Programming multi-core and many-core computing systems Sabri Pllana, Linnaeus University, Sweden Fatos Xhafa, Technical University of Catalonia, Spain Provides state-of-the-art methods for programming multi-core and many-core systems The book comprises a selection of twenty two chapters covering: fundamental techniques and algorithms; programming approaches; methodologies and frameworks; scheduling and management; testing and evaluation methodologies; and case studies for programming multi-core and many-core systems. Program development for multi-core processors, especially for heterogeneous multi-core processors, is significantly more complex than for single-core processors. However, programmers have been traditionally trained for the development of sequential programs, and only a small percentage of them have experience with parallel programming. In the past, only a relatively small group of programmers interested in High Performance Computing (HPC) was concerned with the parallel programming issues, but the situation has changed dramatically with the appearance of multi-core processors on commonly used computing systems. It is expected that with the pervasiveness of multi-core processors, parallel programming will become mainstream. The pervasiveness of multi-core processors affects a large spectrum of systems, from embedded and general-purpose, to high-end computing systems. This book assists programmers in mastering the efficient programming of multi-core systems, which is of paramount importance for the software-intensive industry towards a more effective product-development cycle. Key features: Lessons, challenges, and roadmaps ahead. Contains real world examples and case studies. Helps programmers in mastering the efficient programming of multi-core and many-core systems. The book serves as a reference for a larger audience of practitioners, young researchers and graduate level students. A basic level of programming knowledge is required to use this book. Table of Contents PART I: FOUNDATIONS CHAPTER 1: MULTI- AND MANY-CORES, ARCHITECTURAL OVERVIEW FOR PROGRAMMERS CHAPTER 2: PROGRAMMING MODELS FOR MULTICORE AND MANY-CORE COMPUTING SYSTEMS CHAPTER 3: LOCK-FREE CONCURRENT DATA STRUCTURES CHAPTER 4: SOFTWARE TRANSACTIONAL MEMORY PART II: PROGRAMMING APPROACHES CHAPTER 5: HYBRID/HETEROGENEOUS PROGRAMMING WITH OMPSS AND ITS SOFTWARE/HARDWARE IMPLICATIONS CHAPTER 6: SKELETON PROGRAMMING FOR PORTABLE MANY-CORE COMPUTING CHAPTER 7: DSL STREAM PROGRAMMING ON MULTICORE ARCHITECTURES CHAPTER 8: PROGRAMMING WITH TRANSACTIONAL MEMORY CHAPTER 9: OBJECT-ORIENTED STREAM PROGRAMMING CHAPTER 10: SOFTWARE-BASED SPECULATIVE PARALLELIZATION CHAPTER 11: AUTONOMIC DISTRIBUTION AND ADAPTATION PART III: PROGRAMMING FRAMEWORKS CHAPTER 12: PEPPHER: PERFORMANCE PORTABILITY AND PROGRAMMABILITY FOR HETEROGENEOUS MANY-CORE ARCHITECTURES CHAPTER 13: FASTFLOW: HIGH-LEVEL AND EFFICIENT STREAMING ON MULTICORE CHAPTER 14: PARALLEL PROGRAMMING FRAMEWORK FOR H.264/AVC VIDEO ENCODING IN MULTICORE SYSTEMS CHAPTER 15: PARALLELIZING EVOLUTIONARY ALGORITHMS ON GPGPU CARDS WITH THE EASEA PLATFORM PART IV: TESTINE, EVALUATION AN OPTIMIZATION CHAPTER 16: SMART INTERLEAVINGS FOR TESTING PARALLEL PROGRAMS CHAPTER 17: PARALLEL PERFORMANCE EVALUATION AND OPTIMIZATION CHAPTER 18: A METHODOLOGY FOR OPTIMIZING MULTITHREADED SYSTEM SCALABILITY ON MULTICORES CHAPTER 19: IMPROVING MULTICORE SYSTEM PERFORMANCE THROUGH DATA COMPRESSION PART V: SCHEDULING AND MANAGEMENT CHAPTER 20: PROGRAMMING AND MANAGING RESOURCES ON ACCELERATOR-ENABLED CLUSTERS CHAPTER 21: AN APPROACH FOR EFFICIENT EXECUTION OF SPMD APPLICATIONS ON MULTICORE CLUSTERS CHAPTER 22: OPERATING SYSTEM AND SCHEDULING FOR FUTURE MULTICORE AND MANY-CORE PLATFORMS
python programming
1 Computers and Programs 1 1.1 The Universal Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Program Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 What is Computer Science? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.4 Hardware Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.5 Programming Languages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.6 The Magic of Python . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.7 Inside a Python Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.8 Chaos and Computers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.9 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Writing Simple Programs 13 2.1 The Software Development Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 Example Program: Temperature Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 Elements of Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1 Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.2 Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4 Output Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5 Assignment Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.5.1 Simple Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.5.2 Assigning Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5.3 Simultaneous Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.6 Definite Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.7 Example Program: Future Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.8 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 Computing with Numbers 25 3.1 Numeric Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2 Using the Math Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3 Accumulating Results: Factorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.4 The Limits of Int . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.5 Handling Large Numbers: Long Ints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.6 Type Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.7 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4 Computing with Strings 39 4.1 The String Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.2 Simple String Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.3 Strings and Secret Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.3.1 String Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.3.2 Programming an Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3.3 Programming a Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3.4 Other String Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 i ii CONTENTS 4.3.5 From Encoding to Encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.4 Output as String Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.4.1 Converting Numbers to Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.4.2 String Formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.4.3 Better Change Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.5 File Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.5.1 Multi-Line Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.5.2 File Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.5.3 Example Program: Batch Usernames . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.5.4 Coming Attraction: Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.6 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5 Objects and Graphics 61 5.1 The Object of Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.2 Graphics Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3 Using Graphical Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.4 Graphing Future Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.5 Choosing Coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.6 Interactive Graphics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.6.1 Getting Mouse Clicks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.6.2 Handling Textual Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.7 Graphics Module Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.7.1 GraphWin Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.7.2 Graphics Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.7.3 Entry Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.7.4 Displaying Images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.7.5 Generating Colors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.8 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6 Defining Functions 85 6.1 The Function of Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.2 Functions, Informally . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3 Future Value with a Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.4 Functions and Parameters: The Gory Details . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.5 Functions that Return Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.6 Functions and Program Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.7 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7 Control Structures, Part 1 101 7.1 Simple Decisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.1.1 Example: TemperatureWarnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.1.2 Forming Simple Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.1.3 Example: Conditional Program Execution . . . . . . . . . . . . . . . . . . . . . . . 104 7.2 Two-Way Decisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.3 Multi-Way Decisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7.4 Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7.5 Study in Design: Max of Three . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.5.1 Strategy 1: Compare Each to All . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.5.2 Strategy 2: Decision Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 7.5.3 Strategy 3: Sequential Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7.5.4 Strategy 4: Use Python . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7.5.5 Some Lessons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 7.6 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 CONTENTS iii 8 Control Structures, Part 2 119 8.1 For Loops: A Quick Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8.2 Indefinite Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8.3 Common Loop Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.3.1 Interactive Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.3.2 Sentinel Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.3.3 File Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 8.3.4 Nested Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 8.4 Computing with Booleans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.4.1 Boolean Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.4.2 Boolean Algebra . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8.5 Other Common Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 8.5.1 Post-Test Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 8.5.2 Loop and a Half . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 8.5.3 Boolean Expressions as Decisions . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 8.6 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9 Simulation and Design 137 9.1 Simulating Racquetball . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.1.1 A Simulation Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.1.2 Program Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.2 Random Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.3 Top-Down Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 9.3.1 Top-Level Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 9.3.2 Separation of Concerns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 9.3.3 Second-Level Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.3.4 Designing simNGames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.3.5 Third-Level Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 9.3.6 Finishing Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 9.3.7 Summary of the Design Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 9.4 Bottom-Up Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 9.4.1 Unit Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 9.4.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 9.5 Other Design Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 9.5.1 Prototyping and Spiral Development . . . . . . . . . . . . . . . . . . . . . . . . . . 150 9.5.2 The Art of Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.6 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 10 Defining Classes 155 10.1 Quick Review of Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 10.2 Example Program: Cannonball . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 10.2.1 Program Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 10.2.2 Designing the Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 10.2.3 Modularizing the Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 10.3 Defining New Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 10.3.1 Example: Multi-Sided Dice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 10.3.2 Example: The Projectile Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 10.4 Objects and Encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 10.4.1 Encapsulating Useful Abstractions . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 10.4.2 Putting Classes in Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 10.5 Widget Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 10.5.1 Example Program: Dice Roller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 10.5.2 Building Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 10.5.3 Building Dice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 iv CONTENTS 10.5.4 The Main Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 10.6 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 11 Data Collections 177 11.1 Example Problem: Simple Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.2 Applying Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 11.2.1 Lists are Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 11.2.2 Lists vs. Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 11.2.3 List Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 11.3 Statistics with Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.4 Combining Lists and Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 11.5 Case Study: Python Calculator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 11.5.1 A Calculator as an Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 11.5.2 Constructing the Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 11.5.3 Processing Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 11.6 Non-Sequential Collections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 11.6.1 Dictionary Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 11.6.2 Dictionary Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 11.6.3 Example Program: Word Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . 194 11.7 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 12 Object-Oriented Design 201 12.1 The Process of OOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 12.2 Case Study: Racquetball Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 12.2.1 Candidate Objects and Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 12.2.2 Implementing SimStats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 12.2.3 Implementing RBallGame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 12.2.4 Implementing Player . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 12.2.5 The Complete Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 12.3 Case Study: Dice Poker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12.3.1 Program Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12.3.2 Identifying Candidate Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12.3.3 Implementing the Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 12.3.4 A Text-Based UI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 12.3.5 Developing a GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12.4 OO Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 12.4.1 Encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 12.4.2 Polymorphism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 12.4.3 Inheritance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 12.5 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 13 Algorithm Analysis and Design 225 13.1 Searching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 13.1.1 A Simple Searching Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 13.1.2 Strategy 1: Linear Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 13.1.3 Strategy 2: Binary Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 13.1.4 Comparing Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 13.2 Recursive Problem-Solving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 13.2.1 Recursive Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 13.2.2 Recursive Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 13.2.3 Recursive Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 13.3 Sorting Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 13.3.1 Naive Sorting: Selection Sort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 13.3.2 Divide and Conquer: Merge Sort . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 CONTENTS v 13.3.3 Comparing Sorts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 13.4 Hard Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 13.4.1 Towers of Hanoi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 13.4.2 The Halting Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 13.4.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
区块链实战高并发项目
为什么区块链必须是高并发的？   1. 摩尔定律早已结束 目前，提高并发性是解决人类计算能力的主要方向了。但是并发的编程模型一直受到来自上下两方的压力。 2000年开始之际，人们已经意识到摩尔定律失效了。你...
SystemVerilog Reference Manual 3.1a（中英文版）+最新SV IEEE 标准
Table of Contents Section 1 Introduction to SystemVerilog ...................................................................................................... 1 Section 2 Literal Values.................................................................................................................................. 4 2.1 Introduction (informative) ...............................................................................................................4 2.2 Literal value syntax..........................................................................................................................4 2.3 Integer and logic literals ..................................................................................................................4 2.4 Real literals ......................................................................................................................................5 2.5 Time literals .....................................................................................................................................5 2.6 String literals....................................................................................................................................5 2.7 Array literals ....................................................................................................................................6 2.8 Structure literals ...............................................................................................................................6 Section 3 Data Types....................................................................................................................................... 8 3.1 Introduction (informative) ...............................................................................................................8 3.2 Data type syntax...............................................................................................................................9 3.3 Integer data types ...........................................................................................................................10 3.4 Real and shortreal data types .........................................................................................................11 3.5 Void data type ................................................................................................................................11 3.6 chandle data type ...........................................................................................................................11 3.7 String data type ..............................................................................................................................12 3.8 Event data type...............................................................................................................................16 3.9 User-defined types .........................................................................................................................16 3.10 Enumerations .................................................................................................................................17 3.11 Structures and unions.....................................................................................................................22 3.12 Class...............................................................................................................................................26 3.13 Singular and aggregate types .........................................................................................................27 3.14 Casting ...........................................................................................................................................27 3.15 $cast dynamic casting ....................................................................................................................28 3.16 Bit-stream casting ..........................................................................................................................29 Section 4 Arrays ............................................................................................................................................ 32 4.1 Introduction (informative) .............................................................................................................32 4.2 Packed and unpacked arrays ..........................................................................................................32 4.3 Multiple dimensions ......................................................................................................................33 4.4 Indexing and slicing of arrays........................................................................................................34 4.5 Array querying functions ...............................................................................................................35 4.6 Dynamic arrays ..............................................................................................................................35 4.7 Array assignment ...........................................................................................................................37 4.8 Arrays as arguments.......................................................................................................................38 4.9 Associative arrays ..........................................................................................................................39 4.10 Associative array methods .............................................................................................................41 4.11 Associative array assignment.........................................................................................................44 4.12 Associative array arguments ..........................................................................................................44 4.13 Associative array literals................................................................................................................44 4.14 Queues ...........................................................................................................................................45 4.15 Array manipulation methods .........................................................................................................47 Section 5 Data Declarations ......................................................................................................................... 52 5.1 Introduction (informative) .............................................................................................................52 5.2 Data declaration syntax..................................................................................................................52 5.3 Constants........................................................................................................................................52 Accellera SystemVerilog 3.1a Extensions to Verilog-2001 viii Copyright 2004 Accellera. All rights reserved . 5.4 Variables ........................................................................................................................................53 5.5 Scope and lifetime .........................................................................................................................54 5.6 Nets, regs, and logic.......................................................................................................................55 5.7 Signal aliasing................................................................................................................................56 5.8 Type compatibility .........................................................................................................................58 Section 6 Attributes....................................................................................................................................... 61 6.1 Introduction (informative) .............................................................................................................61 6.2 Default attribute type .....................................................................................................................61 Section 7 Operators and Expressions.......................................................................................................... 62 7.1 Introduction (informative) .............................................................................................................62 7.2 Operator syntax..............................................................................................................................62 7.3 Assignment operators ....................................................................................................................62 7.4 Operations on logic and bit types ..................................................................................................63 7.5 Wild equality and wild inequality..................................................................................................63 7.6 Real operators ................................................................................................................................64 7.7 Size.................................................................................................................................................64 7.8 Sign ................................................................................................................................................64 7.9 Operator precedence and associativity ..........................................................................................64 7.10 Built-in methods ............................................................................................................................65 7.11 Static Prefixes ................................................................................................................................66 7.12 Concatenation ................................................................................................................................67 7.13 Unpacked array expressions ..........................................................................................................67 7.14 Structure expressions .....................................................................................................................68 7.15 Tagged union expressions and member access..............................................................................70 7.16 Aggregate expressions ...................................................................................................................71 7.17 Operator overloading .....................................................................................................................72 7.18 Streaming operators (pack / unpack) .............................................................................................73 7.19 Conditional operator ......................................................................................................................77 7.20 Set membership..............................................................................................................................77 Section 8 Procedural Statements and Control Flow.................................................................................. 79 8.1 Introduction (informative) .............................................................................................................79 8.2 Statements ......................................................................................................................................79 8.3 Blocking and nonblocking assignments ........................................................................................80 8.4 Selection statements.......................................................................................................................81 8.5 Loop statements .............................................................................................................................87 8.6 Jump statements.............................................................................................................................89 8.7 Final blocks....................................................................................................................................89 8.8 Named blocks and statement labels ...............................................................................................90 8.9 Disable ...........................................................................................................................................90 8.10 Event control..................................................................................................................................91 8.11 Level-sensitive sequence controls .................................................................................................93 8.12 Procedural assign and deassign removal .......................................................................................94 Section 9 Processes........................................................................................................................................ 95 9.1 Introduction (informative) .............................................................................................................95 9.2 Combinational logic.......................................................................................................................95 9.3 Latched logic..................................................................................................................................96 9.4 Sequential logic..............................................................................................................................96 9.5 Continuous assignments ................................................................................................................96 9.6 fork...join........................................................................................................................................97 9.7 Process execution threads ..............................................................................................................98 Accellera Extensions to Verilog-2001 SystemVerilog 3.1a Copyright 2004 Accellera. All rights reserved. ix 9.8 Process control ...............................................................................................................................98 9.9 Fine-grain process control ...........................................................................................................100 Section 10 Tasks and Functions................................................................................................................... 102 10.1 Introduction (informative) ...........................................................................................................102 10.2 Tasks ............................................................................................................................................103 10.3 Functions......................................................................................................................................104 10.4 Task and function argument passing ...........................................................................................106 10.5 Import and export functions.........................................................................................................109 Section 11 Classes.......................................................................................................................................... 111 11.1 Introduction (informative) ...........................................................................................................111 11.2 Syntax ..........................................................................................................................................112 11.3 Overview......................................................................................................................................113 11.4 Objects (class instance)................................................................................................................113 11.5 Object properties..........................................................................................................................114 11.6 Object methods ............................................................................................................................114 11.7 Constructors .................................................................................................................................115 11.8 Static class properties...................................................................................................................116 11.9 Static methods..............................................................................................................................116 11.10 This ..............................................................................................................................................116 11.11 Assignment, re-naming and copying ...........................................................................................117 11.12 Inheritance and subclasses ...........................................................................................................118 11.13 Overridden members....................................................................................................................119 11.14 Super ............................................................................................................................................119 11.15 Casting .........................................................................................................................................120 11.16 Chaining constructors ..................................................................................................................120 11.17 Data hiding and encapsulation .....................................................................................................121 11.18 Constant class properties .............................................................................................................121 11.19 Abstract classes and virtual methods ...........................................................................................122 11.20 Polymorphism: dynamic method lookup.....................................................................................123 11.21 Class scope resolution operator :: ................................................................................................123 11.22 Out of block declarations .............................................................................................................124 11.23 Parameterized classes ..................................................................................................................125 11.24 Typedef class ...............................................................................................................................126 11.25 Classes and structures ..................................................................................................................126 11.26 Memory management ..................................................................................................................127 Section 12 Random Constraints .................................................................................................................. 128 12.1 Introduction (informative) ...........................................................................................................128 12.2 Overview......................................................................................................................................128 12.3 Random variables ........................................................................................................................131 12.4 Constraint blocks .........................................................................................................................132 12.5 Randomization methods ..............................................................................................................145 12.6 In-line constraints — randomize() with.......................................................................................147 12.7 Disabling random variables with rand_mode() ...........................................................................148 12.8 Controlling constraints with constraint_mode() ..........................................................................149 12.9 Dynamic constraint modification.................................................................................................150 12.10 In-line random variable control ...................................................................................................150 12.11 Randomization of scope variables — std::randomize()...............................................................151 12.12 Random number system functions and methods .........................................................................153 12.13Random stability ..........................................................................................................................154 12.14 Manually seeding randomize .......................................................................................................156 12.15 Random weighted case — randcase ............................................................................................157 Accellera SystemVerilog 3.1a Extensions to Verilog-2001 x Copyright 2004 Accellera. All rights reserved . 12.16 Random sequence generation — randsequence...........................................................................158 Section 13 Interprocess Synchronization and Communication................................................................ 166 13.1 Introduction (informative) ...........................................................................................................166 13.2 Semaphores ..................................................................................................................................166 13.3 Mailboxes.....................................................................................................................................167 13.4 Parameterized mailboxes .............................................................................................................170 13.5 Event ............................................................................................................................................171 13.6 Event sequencing: wait_order() ...................................................................................................172 13.7 Event variables.............................................................................................................................173 Section 14 Scheduling Semantics................................................................................................................. 176 14.1 Execution of a hardware model and its verification environment ...............................................176 14.2 Event simulation ..........................................................................................................................176 14.3 The stratified event scheduler ......................................................................................................176 14.4 The PLI callback control points...................................................................................................180 Section 15 Clocking Blocks .......................................................................................................................... 181 15.1 Introduction (informative) ...........................................................................................................181 15.2 Clocking block declaration ..........................................................................................................181 15.3 Input and output skews ................................................................................................................183 15.4 Hierarchical expressions ..............................................................................................................184 15.5 Signals in multiple clocking blocks .............................................................................................185 15.6 Clocking block scope and lifetime...............................................................................................185 15.7 Multiple clocking blocks example ...............................................................................................185 15.8 Interfaces and clocking blocks.....................................................................................................186 15.9 Clocking block events..................................................................................................................187 15.10 Cycle delay: ## ............................................................................................................................187 15.11 Default clocking...........................................................................................................................188 15.12 Input sampling .............................................................................................................................189 15.13 Synchronous events .....................................................................................................................189 15.14 Synchronous drives......................................................................................................................190 Section 16 Program Block............................................................................................................................ 193 16.1 Introduction (informative) ...........................................................................................................193 16.2 The program construct .................................................................................................................193 16.3 Multiple programs........................................................................................................................195 16.4 Eliminating testbench races .........................................................................................................195 16.5 Blocking tasks in cycle/event mode.............................................................................................196 16.6 Program control tasks ..................................................................................................................196 Section 17 Assertions ................................................................................................................................... 198 17.1 Introduction (informative) ...........................................................................................................198 17.2 Immediate assertions....................................................................................................................198 17.3 Concurrent assertions overview...................................................................................................200 17.4 Boolean expressions ....................................................................................................................201 17.5 Sequences.....................................................................................................................................203 17.6 Declaring sequences ....................................................................................................................206 17.7 Sequence operations ....................................................................................................................208 17.8 Manipulating data in a sequence..................................................................................................224 17.9 Calling subroutines on match of a sequence................................................................................228 17.10 System functions..........................................................................................................................229 17.11 Declaring properties.....................................................................................................................229 17.12 Multiple clock support .................................................................................................................240 Accellera Extensions to Verilog-2001 SystemVerilog 3.1a Copyright 2004 Accellera. All rights reserved. xi 17.13 Concurrent assertions...................................................................................................................246 17.14 Clock resolution ...........................................................................................................................252 17.15 Binding properties to scopes or instances....................................................................................258 17.16 The expect statement ...................................................................................................................259 Section 18 Hierarchy..................................................................................................................................... 261 18.1 Introduction (informative) ...........................................................................................................261 18.2 Packages.......................................................................................................................................261 18.3 Compilation unit support .............................................................................................................265 18.4 Top-level instance........................................................................................................................266 18.5 Module declarations.....................................................................................................................267 18.6 Nested modules............................................................................................................................267 18.7 Extern modules ............................................................................................................................269 18.8 Port declarations ..........................................................................................................................270 18.9 List of port expressions................................................................................................................271 18.10 Time unit and precision ...............................................................................................................271 18.11 Module instances .........................................................................................................................272 18.12 Port connection rules ...................................................................................................................276 18.13 Name spaces ................................................................................................................................277 18.14 Hierarchical names ......................................................................................................................278 Section 19 Interfaces ..................................................................................................................................... 279 19.1 Introduction (informative) ...........................................................................................................279 19.2 Interface syntax............................................................................................................................280 19.3 Ports in interfaces.........................................................................................................................284 19.4 Modports ......................................................................................................................................285 19.5 Interfaces and specify blocks .......................................................................................................291 19.6 Tasks and functions in interfaces.................................................................................................291 19.7 Parameterized interfaces ..............................................................................................................297 19.8 Virtual interfaces..........................................................................................................................299 19.9 Access to interface objects...........................................................................................................303 Section 20 Coverage...................................................................................................................................... 305 20.1 Introduction (informative) ...........................................................................................................305 20.2 Defining the coverage model: covergroup...................................................................................306 20.3 Using covergroup in classes ........................................................................................................308 20.4 Defining coverage points .............................................................................................................309 20.5 Defining cross coverage...............................................................................................................315 20.6 Specifying coverage options ........................................................................................................319 20.7 Predefined coverage methods ......................................................................................................324 20.8 Predefined coverage system tasks and functions .........................................................................324 20.9 Organization of option and type_option members ......................................................................324 Section 21 Parameters .................................................................................................................................. 326 21.1 Introduction (informative) ...........................................................................................................326 21.2 Parameter declaration syntax .......................................................................................................327 Section 22 Configuration Libraries............................................................................................................. 330 22.1 Introduction (informative) ...........................................................................................................330 22.2 Libraries .......................................................................................................................................330 Section 23 System Tasks and System Functions ........................................................................................ 331 23.1 Introduction (informative) ...........................................................................................................331 23.2 Elaboration-time typeof function.................................................................................................331 Accellera SystemVerilog 3.1a Extensions to Verilog-2001 xii Copyright 2004 Accellera. All rights reserved . 23.3 Typename function ......................................................................................................................331 23.4 Expression size system function ..................................................................................................332 23.5 Range system function.................................................................................................................333 23.6 Shortreal conversions...................................................................................................................333 23.7 Array querying system functions .................................................................................................334 23.8 Assertion severity system tasks ...................................................................................................335 23.9 Assertion control system tasks.....................................................................................................336 23.10 Assertion system functions ..........................................................................................................336 23.11 Random number system functions...............................................................................................337 23.12 Program control ...........................................................................................................................337 23.13 Coverage system functions ..........................................................................................................337 23.14 Enhancements to Verilog-2001 system tasks ..............................................................................337 23.15 $readmemb and $readmemh........................................................................................................338 23.16 $writememb and $writememh .....................................................................................................338 23.17 File format considerations for multi-dimensional unpacked arrays ............................................339 23.18 System task arguments for multi-dimensional unpacked arrays .................................................340 Section 24 VCD Data .................................................................................................................................... 342 Section 25 Compiler Directives.................................................................................................................... 343 25.1 Introduction (informative) ...........................................................................................................343 25.2 ‘define macros..............................................................................................................................343 25.3 `include ........................................................................................................................................344 Section 26 Features under consideration for removal from SystemVerilog ........................................... 345 26.1 Introduction (informative) ...........................................................................................................345 26.2 Defparam statements....................................................................................................................345 26.3 Procedural assign and deassign statements..................................................................................345 Section 27 Direct Programming Interface (DPI) ....................................................................................... 347 27.1 Overview......................................................................................................................................347 27.2 Two layers of the DPI ..................................................................................................................348 27.3 Global name space of imported and exported functions..............................................................349 27.4 Imported tasks and functions .......................................................................................................349 27.5 Calling imported functions ..........................................................................................................355 27.6 Exported functions .......................................................................................................................356 27.7 Exported tasks..............................................................................................................................357 27.8 Disabling DPI tasks and functions...............................................................................................357 Section 28 SystemVerilog Assertion API .................................................................................................... 359 28.1 Requirements ...............................................................................................................................359 28.2 Extensions to VPI enumerations..................................................................................................359 28.3 Static information ........................................................................................................................360 28.4 Dynamic information ...................................................................................................................363 28.5 Control functions .........................................................................................................................366 Section 29 SystemVerilog Coverage API .................................................................................................... 368 29.1 Requirements ...............................................................................................................................368 29.2 SystemVerilog real-time coverage access ...................................................................................369 29.3 FSM recognition ..........................................................................................................................374 29.4 VPI coverage extensions..............................................................................................................377 Section 30 SystemVerilog Data Read API .................................................................................................. 381 30.1 Introduction (informative) ...........................................................................................................381 Accellera Extensions to Verilog-2001 SystemVerilog 3.1a Copyright 2004 Accellera. All rights reserved. xiii 30.2 Requirements ...............................................................................................................................381 30.3 Extensions to VPI enumerations..................................................................................................382 30.4 VPI object type additions.............................................................................................................383 30.5 Object model diagrams ................................................................................................................385 30.6 Usage extensions to VPI routines ................................................................................................387 30.7 VPI routines added in SystemVerilog .........................................................................................388 30.8 Reading data ................................................................................................................................389 30.9 Optionally unloading the data......................................................................................................399 30.10 Reading data from multiple databases and/or different read library providers ...........................399 30.11VPI routines extended in SystemVerilog.....................................................................................402 30.12VPI routines added in SystemVerilog .........................................................................................403 Section 31 SystemVerilog VPI Object Model............................................................................................. 407 31.1 Introduction (informative) ...........................................................................................................407 31.2 Instance .......................................................................................................................................409 31.3 Interface ......................................................................................................................................410 31.4 Program........................................................................................................................................410 31.5 Module (supersedes IEEE 1364-2001 26.6.1) ............................................................................411 31.6 Modport ......................................................................................................................................412 31.7 Interface tf decl ............................................................................................................................412 31.8 Ports (supersedes IEEE 1364-2001 26.6.5) .................................................................................413 31.9 Ref Obj.........................................................................................................................................414 31.10 Variables (supersedes IEEE 1364-2001 section 26.6.8) .............................................................416 31.11 Var Select (supersedes IEEE 1364-2001 26.6.8).........................................................................418 31.12 Typespec ......................................................................................................................................419 31.13 Variable Drivers and Loads (supersedes IEEE 1364-2001 26.6.23) ...........................................421 31.14 Instance Arrays (supersedes IEEE 1364-2001 26.6.2) ................................................................421 31.15 Scope (supersedes IEEE 1364-2001 26.6.3) ...............................................................................422 31.16 IO Declaration (supersedes IEEE 1364-2001 26.6.4) .................................................................423 31.17 Clocking Block ...........................................................................................................................424 31.18 Class Object Definition................................................................................................................425 31.19 Constraint, constraint ordering, distribution, ...............................................................................426 31.20 Constraint expression...................................................................................................................427 31.21 Class Variables ...........................................................................................................................428 31.23 Named Events (supersedes IEEE 1364-2001 26.6.11) ................................................................430 31.24 Task, Function Declaration (supersedes IEEE 1364-2001 26.6.18)............................................431 31.25 Alias Statement ...........................................................................................................................432 31.26 Frames (supersedes IEEE 1364-2001 26.6.20)............................................................................433 31.27 Threads.........................................................................................................................................434 31.28 tf call (supersedes IEEE 1364-2001 26.6.19) ..............................................................................435 31.29 Module path, path term (supersedes IEEE 1364-2001 26.6.15) .................................................436 31.30 Concurrent assertions ..................................................................................................................437 31.31 Property Decl ..............................................................................................................................437 31.32 Property Specification .................................................................................................................438 31.33 Multiclock Sequence Expression ................................................................................................439 31.34 Sequence Declaration .................................................................................................................440 31.35 Sequence Expression ..................................................................................................................441 31.36 Attribute (supersedes IEEE 1364-2001 26.6.42) ........................................................................442 31.37 Atomic Statement (supersedes IEEE 1364-2001 26.6.27) .........................................................443 31.38 If, if else, return, case, do while (supersedes IEEE 1364-2001 26.6.35, 26.6.36).......................444 31.39 waits, disables, expect, foreach (supersedes IEEE 1364 26.6.38) ...............................................445 31.40 Simple expressions (supersedes IEEE 1364-2001 26.6.25) ........................................................446 31.41 Expressions (supersedes IEEE 1364-2001 26.6.26) ....................................................................447 31.42 Event control (supersedes IEEE 1364-2001 26.6.30)..................................................................448 Accellera SystemVerilog 3.1a Extensions to Verilog-2001 xiv Copyright 2004 Accellera. All rights reserved . 31.43 Event stmt (supersedes IEEE 1364-2001 26.6.27) .....................................................................448 31.44 Process (supersedes IEEE 1364-2001 26.6.27) ..........................................................................449 31.45 Assignment (supersedes IEEE 1364-2001 26.6.28) ...................................................................449 Annex A Formal Syntax.............................................................................................................................. 451 Annex B Keywords ...................................................................................................................................... 488 Annex C Std Package ................................................................................................................................. 490 Annex D Linked Lists................................................................................................................................. 492 Annex E DPI C-layer .................................................................................................................................. 498 Annex F Include files .................................................................................................................................. 523 Annex G Inclusion of Foreign Language Code ......................................................................................... 529 Annex H Formal Semantics of Concurrent Assertions ............................................................................ 533 Annex I sv_vpi_user.h................................................................................................................................ 544 Annex J Glossary ........................................................................................................................................ 553 Annex K Bibliography................................................................................................................................. 555 Index 557
Hive Vectorized Query Execution Design
Hive Vectorized Query Execution Design Jitendra Pandey†, Eric Hanson‡, Owen O’Malley†, Remus Rusanu‡, Sarvesh Sakalanaga‡, Teddy Choi †Hortonworks, ‡Microsoft 9/17/13 目录 Introduction Basic Idea Incremental modifications to Hive execution engine.
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