library ieee;
use ieee.std_logic_1164.all;
--the system CLOCK is 5秒
entity abc is
port(
CLOCK:IN STD_LOGIC;-- 输入时钟
RESET:INSTD_LOGIC;-- 复位信号
r,g,y:OUT STD_LOGIC);-- 红绿黄信号
END abc;
architecture imp of abc is
signal cnt:STD_LOGIC_VECTOR(3 downto 0); -- 计数器;
begin
p1:process (RESET,clock)
begin
if RESET = '1' then -- Initilaize all the signals;
r<='0';
g<='0';
y<='0';
cnt<="0000";
elsif (clock'event and clock='1') then
if(cnt<"1110") then
cnt<=cnt+1;
else
cnt<="0000";
end if;
if(cnt="0000") then
r<='0';
g<='0';
y<='1';--黄亮
elsif(cnt="0001") then
r<='0';
g<='1';--绿亮
y<='0';
elsif(cnt="0111") then
r<='0';
g<='0';
y<='1';--黄亮
elsif(cnt="1000") then
r<='1';--红亮
g<='0';
y<='0';
end if;
end if;
end process p1;
end imp;