SCS user

andy12223618 2009-06-19 04:23:23
想问一下,如果我把所有的scs需要的服务都装在一台机器上,并且一切的服务都只用一个帐号安装,是administrator,那么scs user应该是administrator。然后所有的其它的服务是不是我都可以只用这一个帐号来做。
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Duofeng 2009-06-26
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很难说, 都有可能

可以试试linux下串口输出,那个不需要AMT驱动就可以 ,可以在linux 内核加启动参数 console = ttyS1 (一般是ttyS1,如果主板有一个物理串口情况下, 没有物理串口则是ttyS0)
Duofeng 2009-06-23
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应该是可以的. 我这边测试的时候是新建了一个SCS用户,带administrator权限,然后所有的SCS相关的操作都是基于这个用户,是没有问题的。
andy12223618 2009-06-23
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我想问一下,现在我们正在测试6.0,遇到很多的问题。
开始配置成功之后,提示configured,但是没有办法实现remote control。
使用串口调试工具来查看的时候,发现com3口,虽然往里写入数据,在接收的窗口看不到数据。拿上市机器来对照,发现往com3口写入数据,然后还能读取出来,在窗口显示,这种问题是驱动的问题,还是硬件本身的问题。
2440 硬件手册 INTRODUCTION This user’s manual describes SAMSUNG's S3C2440A 16/32-bit RISC microprocessor. SAMSUNG’s S3C2440A is designed to provide hand-held devices and general applications with low-power, and high-performance microcontroller solution in small die size. To reduce total system cost, the S3C2440A includes the following components. The S3C2440A is developed with ARM920T core, 0.13um CMOS standard cells and a memory complier. Its lowpower, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive applications. It adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA). The S3C2440A offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length. By providing a complete set of common system peripherals, the S3C2440A minimizes overall system costs and eliminates the need to configure additional components. The integrated on-chip functions that are described in this document include: · Around 1.2V internal, 1.8V/2.5V/3.3V memory, 3.3V external I/O microprocessor with 16KB I-Cache/16KB DCache/ MMU · External memory controller (SDRAM Control and Chip Select logic) · LCD controller (up to 4K color STN and 256K color TFT) with LCD-dedicated DMA · 4-ch DMA controllers with external request pins · 3-ch UARTs (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO) · 2-ch SPls · IIC bus interface (multi-master support) · IIS Audio CODEC interface · AC’97 CODEC interface · SD Host interface version 1.0 & MMC Protocol version 2.11 compatible · 2-ch USB Host controller / 1-ch USB Device controller (ver 1.1) · 4-ch PWM timers / 1-ch Internal timer / Watch Dog Timer · 8-ch 10-bit ADC and Touch screen interface · RTC with calendar function · Camera interface (Max. 4096 x 4096 pixels input support. 2048 x 2048 pixel input support for scaling) · 130 General Purpose I/O ports / 24-ch external interrupt source · Power control: Normal, Slow, Idle and Sleep mode · On-chip clock generator with PLL

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