大家来找茬儿之——PLI程序编译装载后modelsim崩溃

[aboy85]

今天写了个pli程序，编译、生成dll文件都没有问题，就是仿真装载过程中，modelsim崩溃，请大家给分析一下，这是什么病，怎么治！源码如下：
top.v

`timescale 1ns/1ns
module top(clk,AM,AS,WRITE,IACK,LWORD,DS0,DS1,DTACK,BERR,RETRY,AB,DB,SYSRESET);
output clk;
output[5:0] AM;
output AS;
output WRITE;
output IACK;
output LWORD;
output DS0;
output DS1;
output DTACK;
output BERR;
output RETRY;
output [31:1] AB;
output [31:0] DB;
output SYSRESET;

reg clk;
reg [5:0] AM;
reg AS;
reg WRITE;
reg IACK;
reg LWORD;
reg DS0;
reg DS1;
reg DTACK;
reg BERR;
reg RETRY;
reg [31:1] AB;
reg [31:0] DB;
reg SYSRESET;
initial
begin
$clkGen(clk);
assign SYSRESET = 0;
assign WRITE = 1;
#20 assign SYSRESET = 1;
end

always @(posedge clk)
begin
// Connect the Master
$simMaster(AM,AS,WRITE,IACK,LWORD,DS0,DS1,AB,DB,SYSRESET,DTACK,BERR);
// Connect the Slave
//simSlave slave(.clk(clk),.Write(WRITE),.DTACK(DTACK),.AB(AB),.DB(DB));

end

endmodule

clkGen.c:
#include "acc_user.h"
#include "veriuser.h"
#include <malloc.h>

// Define the ON and OFF time of clock
#define PERIOD 5

extern int clkGen();
extern int clkInit();
extern int clkReactive (int data, int reason, int paramvc);

// Data structure
struct clkData {
int clk;
int clkCnt;
};
struct clkData *data;

// Main routine which toggles the clock
int clkGen ()
{
acc_initialize();
// Get the stored workarea
data = ( struct clkData * )tf_igetworkarea(tf_getinstance());
if (data->clkCnt == PERIOD)
{
data->clk = (data->clk == 0) ? 1 : 0;
data->clkCnt = 0;
io_printf("%d Current clk = %d\n",tf_gettime(), data->clk);
// Drive the clock signal in HDL
tf_putp (1, data->clk);
}
else
{
data->clkCnt ++;
}
tf_setdelay(1);
acc_close();
return 0;
}

// checktf() routine
// This function inits the objects and also stores the object in workarea
int clkInit()
{
acc_initialize();
data = ( struct clkData * )malloc( sizeof( struct clkData ) );
data->clkCnt = 0;
data->clk = 0;
tf_setworkarea(data);
acc_close();
return 0;
}

// misctf() routine
// This routine is called after 1 tick
int clkReactive (int data, int reason, int paramvc)
{
acc_initialize();
// if callback reason is reactive, then call clkGen function
if (reason == reason_reactivate)
{
clkGen();
// Set the callback delay to 1 tick
}
acc_close();
return 0;
}


s_tfcell veriusertfs[] = {
{usertask, 0, clkInit, 0, clkGen, clkReactive, "$clkGen"},
{0}
};

simMaster.c:
#include "acc_user.h"
#include "veriuser.h"
#include <stdio.h>
#include <string.h>
#include <malloc.h>



// Data structure
typedef struct myMaster
{
handle WRITE;
handle SYSRESET;
int error;
int error_time;
int numCount;
int indexCount;
int state;
int write_value;
int sysreset_value;
int regAdd[10];
} myMaster_s,*myMaster_p;

myMaster_p master;


int master_checktf()
{
acc_initialize();
FILE *fp;
master = (myMaster_p ) malloc (sizeof(myMaster_p));
master->error = 0;
master->error_time = 0;
master->state = 0;
master->numCount = 0;
master->indexCount = 0;
master->write_value = 0;
master->sysreset_value = 0;
fp = fopen("data.txt", "r");
if(fp == NULL)
{
return 0;
}
else
{
while(!feof(fp))
{
fscanf(fp,"%d",&(master->regAdd[master->numCount]));
master->numCount = master->numCount +1;
}
}
fclose(fp);
tf_setworkarea((char *)master);
acc_close();
return 0;
}



//
int master_calltf(int data, int reason)
{
acc_initialize();
io_printf("------------------%2d enter master_calltf-----------------\n",tf_gettime());
tf_synchronize( );
acc_close();
return 0;
}

void masterState()
{
master = (myMaster_p ) tf_igetworkarea(tf_getinstance());
master->WRITE = acc_handle_tfarg(3);
master->write_value = value_str_to_int(acc_fetch_value(master->WRITE, "%d", 0));
master->SYSRESET = acc_handle_tfarg(10);
master->sysreset_value = value_str_to_int(acc_fetch_value(master->SYSRESET, "%d", 0));
io_printf("------------------%2d enter masterState--------------------\n",tf_gettime());
if(master->sysreset_value == 0)
{
//AM = 0
tf_putp(1,0);
//AS = 1
tf_putp(2,1);
//LWORD = 1
tf_putp(5,1);
//DS0 = 1
tf_putp(6,1);
//DS1 = 1
tf_putp(7,1);
//AB = 0
tf_putp(8,0);
}
else if(master->indexCount < master->numCount)
{
switch(master->state)
{
//IDLE
case 0:
{
//AM = 09H
tf_putp(1,9);
//AS = 0
tf_putp(2,0);
//LWORD = 0
tf_putp(5,0);
//DS0 = 0
tf_putp(6,0);
//DS1 = 0
tf_putp(7,0);
//AB = regADD[indexcount]
tf_putp(8,master->regAdd[master->indexCount]);//AB
master->indexCount = master->indexCount + 1;
io_printf("**************addr placed on bus**************************\n",tf_gettime());
if(master->write_value == 0)
{
master->state = 1;
}
else
{
master->state = 2;
}
break;
}
case 1://WAIT_READ

break;
case 2://READ
break;
default:
master->state = 0;//IDLE
break;
}
}
else
{
tf_dofinish();
}
display(master);
}

// misctf() routine
//
int master_misctf (int data, int reason, int paramvc)
{
acc_initialize();
io_printf("--------------%2d enter master_misctf---------------------\n",tf_gettime());
if (reason == reason_synch)
{
// Call the masterState to modify state
masterState ();
}
// Print simulation stats when $finish is called
if (reason == reason_finish)
{
master = (myMaster_p ) tf_igetworkarea(tf_getinstance());
io_printf("=========================================\n");
if (master->error != 0)
{
io_printf (" Simulation : FAILED\n");
io_printf (" Mismatched %d\n",master->error);
io_printf (" First Mismatch at time %d\n", master->error_time);
}
else
{
io_printf (" Simulation : PASSED\n");
}
io_printf("=========================================\n");
}
acc_close();
return 0;
}


int value_str_to_int(char * value)
{
if((strcmp(value,"0"))==0)
{
return 0;
}
else if((strcmp(value,"1"))==0)
{
return 1;
}
else
{
return -1;
}
}

//display message
int display(myMaster_p master)
{
io_printf("--------------current time = %2d----------------\n",tf_gettime());
io_printf("--------------master->numCount = %2d----------------\n",master->numCount);
io_printf("--------------master->indexCount = %2d----------------\n",master->indexCount);
io_printf("--------------master->state = %2d----------------\n",master->state);
io_printf("--------------master->write_value = %2d----------------\n",master->write_value);
io_printf("--------------master->sysreset_value = %2d----------------\n",master->sysreset_value);
return 0;
}

s_tfcell veriusertfs[] = {
{usertask, 0, master_checktf, 0, master_calltf, master_misctf, "$simMaster"},
{0}
};