verilog case语句嵌套

[ggg1986123567]

always@(posedge iCLK or negedge iRST)
if(!iRST)
max <= 200;
else
begin//1
case(Distance_range)
3:begin
case(Dist_thresh)
3:max<=max_thresh*3>>3; // 6/16
0:max<=(max_thresh*5)>>4; // 5/16
1:max<=max_thresh>>2; // 4/16
2:max<=(max_thresh*3)>>4; // 3/16
4:max<=max_thresh>>3; // 2/16
default:max<=diffaim_S;
endcase
end


0: begin
case(Dist_thresh)
3:max<=(max_thresh*7)>>4; // 7/16
0:max<=(max_thresh*3)>>3;
107336722 16:22:02
// 6/16
1:max<=(max_thresh*5)>>4; // 5/16
2:max<=max_thresh>>2; // 4/16
4:max<=(max_thresh*3)>>4; // 3/16
default:max<=diffaim_S;
endcase
end

[size=11px]上述代码中case语句中变量Distance_range和Dist_thresh都是3位的，现在不想使用case语句嵌套，想把两个变量放在一条case语句里，应该怎么改写呢？希望各位大侠给予指点！[/size]

[lgy198612]

Distance_range 这个变量可以不用CASE，IF /ELSE不就能搞定了 ，把两个变量放在一条case语句里更乱又麻烦