使用Vtune如何确定l2 cache miss占resource stall的比例

[电力信息系统]

如题：
使用vtune软件，得到如下结果：
l2 cache miss rate 0.08
resource stall ratio 0.94

resource_stalls.any 17,390,106,558
l2_line_in_self.any 174.128.064

请问如何计算l2 cache miss对resource stall的比例呢？

[intel_zhenyuwang]

L2_LINES_IN 指所有的L2 Cache Misses，包含Instruction Prefetch中发生的Miss

建议用MEM_LOAD_RETIRED.L2_MISS， 见下表包含所有的Stall


About Stall Events
This group contains events that monitor various stall conditions.


Symbol Name Event Code Description
DELAYED_BYPASS.FP
0x19
Delayed bypass to FP operation.

DELAYED_BYPASS.LOAD
0x19
Delayed bypass to load operation.

DELAYED_BYPASS.SIMD
0x19
Delayed bypass to SIMD operation.

LOAD_BLOCK.L1D
0x03
Loads blocked by the L1 data cache.

LOAD_BLOCK.OVERLAP_STORE
0x03
Loads that partially overlap an earlier store, or 4K aliased with a previous store.

LOAD_BLOCK.STA
0x03
Loads blocked by a preceding store with unknown address.

LOAD_BLOCK.STD
0x03
Loads blocked by a preceding store with unknown data.

LOAD_BLOCK.UNTIL_RETIRE
0x03
Loads blocked until retirement.

MACHINE_NUKES.MEM_ORDER
0xC3
Execution pipeline restart due to memory ordering conflict or memory disambiguation misprediction.

MACHINE_NUKES.SMC
0xC3
Self-Modifying Code detected.

MEM_LOAD_RETIRED.DTLB_MISS
0xCB
Retired loads that miss the DTLB (precise event).

MEM_LOAD_RETIRED.L1D_LINE_MISS
0xCB
L1 data cache line missed by retired loads (precise event).

MEM_LOAD_RETIRED.L1D_MISS
0xCB
Retired loads that miss the L1 data cache (precise event).

MEM_LOAD_RETIRED.L2_LINE_MISS
0xCB
L2 cache line missed by retired loads (precise event).

MEM_LOAD_RETIRED.L2_MISS
0xCB
Retired loads that miss the L2 cache (precise event).

RAT_STALLS.ANY
0xD2
All RAT stall cycles.

RAT_STALLS.FLAGS
0xD2
Flag stall cycles.

RAT_STALLS.FLAGS_COUNT
0xD2
Flag stall events.

RAT_STALLS.FPSW
0xD2
FPU status word stall.

RAT_STALLS.PARTIAL_COUNT
0xD2
Partial register stall events.

RAT_STALLS.PARTIAL_CYCLES
0xD2
Partial register stall cycles.

RAT_STALLS.ROB_READ_PORT
0xD2
ROB read port stalls cycles.

RESOURCE_STALLS.ANY
0xDC
Resource related stalls.

RESOURCE_STALLS.BR_MISS_CLEAR
0xDC
Cycles stalled due to branch misprediction.

RESOURCE_STALLS.FPCW
0xDC
Cycles stalled due to FPU control word write.

RESOURCE_STALLS.LD_ST
0xDC
Cycles during which the pipeline has exceeded load or store limit or waiting to commit all stores.

RESOURCE_STALLS.ROB_FULL
0xDC
Cycles during which the ROB is full.

RESOURCE_STALLS.RS_FULL
0xDC
Cycles during which the RS is full.

SB_DRAIN_CYCLES
0x04
Cycles while stores are blocked due to store buffer drain.

STORE_BLOCK.ORDER
0x04
Cycles while store is waiting for a preceding store to be globally observed.

STORE_BLOCK.SNOOP
0x04
A store is blocked due to a conflict with an external or internal snoop.

[popxiha]

最后ichi··········123

[电力信息系统]

stall由很多原因组成，如何得到那个所占stall的比例呢？

[intel_zhenyuwang]

4楼，列表中的一个(如MEM_LOAD_RETIRED.L2_LINE_MISS)除以总的Resource Stall

[电力信息系统]

MEM_LOAD_RETIRED.L2_LINE_MISS EVENTS 20
Resource Stall.any events 100

那结果是20/100？

[intel_zhenyuwang]

[Quote=引用 6 楼 zhouguoling 的回复:]
MEM_LOAD_RETIRED.L2_LINE_MISS EVENTS 20
Resource Stall.any events 100

那结果是20/100？
[/Quote]就是这个意思

[电力信息系统]

MEM_LOAD_RETIRED.L2_LINE_MISS
0xCB
L2 cache line missed by retired loads (precise event).

MEM_LOAD_RETIRED.L2_MISS
0xCB
Retired loads that miss the L2 cache (precise event).
通过VTUNE测量出来的上面两个的单位是什么呢？
RESOURCE_STALLS.ANY 是cycles

[intel_zhenyuwang]

[Quote=引用 8 楼 zhouguoling 的回复:]
MEM_LOAD_RETIRED.L2_LINE_MISS
0xCB
L2 cache line missed by retired loads (precise event).

MEM_LOAD_RETIRED.L2_MISS
0xCB
Retired loads that miss the L2 cache (precise event).
通过VTUNE测量出来的上面两个的单位是什么呢？
RESOURCE_STALLS.ANY 是cycles
[/Quote]
对所有的Events来说，VTune(TM) Analyzer 得到的是Samples, Event Count number = Samples*SAV (Sample After Value)