VHDL语言，关于端口映射问题

[leileipei]

我的程序是全家器的，出现了以下错误，请各位帮忙解决下。
LIBRARY IEEE; --or
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY or2 IS
PORT(a,b : IN STD_LOGIC;
c : OUT STD_LOGIC);
END ENTITY or2;
ARCHITECTURE fu1 OF or2 IS
BEGIN
c <= a OR b;
END ARCHITECTURE fu1;

LIBRARY IEEE; --h_adder
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY h_adder IS
PORT(a,b : IN STD_LOGIC; co,so : OUT STD_LOGIC);
END ENTITY h_adder;
ARCHITECTURE fh1 OF h_adder IS
BEGIN
co <= NOT (a NAND b);
so <= (a NAND b) AND (a OR b);
END ARCHITECTURE fh1;

LIBRARY IEEE; --f_adder
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY f_adder IS
PORT(ain,bin,cin : IN STD_LOGIC; cout,sum : OUT STD_LOGIC);
END ENTITY f_adder;
ARCHITECTURE fd1 OF f_adder IS
COMPONENT h_adder
PORT(a,b : IN STD_LOGIC; co,so : OUT STD_LOGIC);
END COMPONENT;
COMPONENT or2
PORT(a,b : IN STD_LOGIC; c : OUT STD_LOGIC);
END COMPONENT;
SIGNAL d,e,f : STD_LOGIC;
BEGIN
u1 : h_adder PORT MAP (a => ain, b => bin,co => d, so => e);
u2 : h_adder PORT MAP (a => e, b => cin,co => f, so => sum);
u3 : or2 PORT MAP (a => d, b => f, c => cout);
END ARCHITECTURE fd1;

编译后结果是：
Error: Port "a" does not exist in primitive "or2" of instance "u3"
Error: Port "b" does not exist in primitive "or2" of instance "u3"
Error: Port "c" does not exist in primitive "or2" of instance "u3"
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 1 warning