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;XTAL_SEL SETA 12000000
XTAL_SEL SETA 16934400
;FCLK SETA 400000000
FCLK SETA 399651840
[ FCLK = 399651840
M_MDIV EQU 110 ;Fin=16.9344MHz
M_PDIV EQU 3
[ CPU_SEL = 32440001
M_SDIV EQU 1 ; 2440A
|
M_SDIV EQU 0 ; 2440X
]
]
//#define FIN (12000000)
#define FIN (16934400)
com ==================
com Filename: 2440Anorom.ini
com 2003. 5. xx 1st draft.
com 2004. 3. 4 edited for S3C2440A
com ==================
com For S3C2440A
com SDRAM_Little_32, 64MB
com FCLK:101.25MHz UPLL:48MHz
com SDRAM refresh: 64ms(8Kcycle) -> 7.8us
swat $vector_catch 0x00
swat $semihosting_enabled 0x00
swat psr %IFt_SVC
com swat psr %IF_SVC32
com [disable Watch-Dog reset]
swat *0x53000000 0
com << Clock setting >>
com [PLL lock time setting maximum]
swat *0x4c000000 ((0xfff<<12)+(0xfff<<0))
com FCLK:HCLK:PCLK=1:3:6.
swat *0x4c000014 ((0<<2)+(3<<1)+(1))
com [FCLK PMS setting:294.9140MHz -> 0x7f,2,2]
swat *0x4c000004 ((0x61<<12)+(0x1<<4)+(0x2<<0))
com [UCLK PMS setting:48MHz -> 0x78,2,3]
swat *0x4c000008 ((0x40<<12)+(0x4<<4)+(0x2<<0))
com << Memory setting >>
com [Bank6/7: 32-bit bus width]
swat *0x48000000 0x22000000
com [Bank0-5: Access cycle: 14-clocks, others:0-clock]
swat *0x48000004 ((0<<13)+(0<<11)+(7<<8)+(0<<6)+(0<<4)+(0<<2)+0)
swat *0x48000008 ((0<<13)+(0<<11)+(7<<8)+(0<<6)+(0<<4)+(0<<2)+0)
swat *0x4800000c ((0<<13)+(0<<11)+(7<<8)+(0<<6)+(0<<4)+(0<<2)+0)
swat *0x48000010 ((0<<13)+(0<<11)+(7<<8)+(0<<6)+(0<<4)+(0<<2)+0)
swat *0x48000014 ((0<<13)+(0<<11)+(7<<8)+(0<<6)+(0<<4)+(0<<2)+0)
swat *0x48000018 ((0<<13)+(0<<11)+(7<<8)+(0<<6)+(0<<4)+(0<<2)+0)
com [Bank6/7: SDRAM, Trcd:2clock, CA:9-bit]
swat *0x4800001c ((3<<15)+(0<<2)+1)
swat *0x48000020 ((3<<15)+(0<<2)+1)
com [SDRAM refresh enable, Trp=2clk, Trc=5clk, Refresh:1654]
swat *0x48000024 ((1<<23)+(0<<22)+(0<<20)+(1<<18)+1654)
com [SCKE_EN enable, SCLK_EN enable, Bank6/7 memory map: 64MB/64MB]
swat *0x48000028 (0x1+(1<<5)+(1<<4))
com [Bank6/7 CL: 3-clocks]
swat *0x4800002c 0x30
swat *0x48000030 0x30
static void cal_cpu_bus_clk(void)
{
U32 val;
U8 m, p, s;
val = rMPLLCON;
m = (val>>12)&0xff;
p = (val>>4)&0x3f;
s = val&3;
//(m+8)*FIN*2 不要超出32位数!
FCLK = ((m+8)*(FIN/100)*2)/((p+2)*(1<<s))*100;
val = rCLKDIVN;
m = (val>>1)&3;
p = val&1;
val = rCAMDIVN;
s = val>>8;
switch (m) {
case 0:
HCLK = FCLK;
break;
case 1:
HCLK = FCLK>>1;
break;
case 2:
if(s&2)
HCLK = FCLK>>3;
else
HCLK = FCLK>>2;
break;
case 3:
if(s&1)
HCLK = FCLK/6;
else
HCLK = FCLK/3;
break;
}
if(p)
PCLK = HCLK>>1;
else
PCLK = HCLK;
if(s&0x10)
cpu_freq = HCLK;
else
cpu_freq = FCLK;
val = rUPLLCON;
m = (val>>12)&0xff;
p = (val>>4)&0x3f;
s = val&3;
UPLL = ((m+8)*FIN)/((p+2)*(1<<s));
if(UPLL==96*MEGA)
rCLKDIVN |= 8; //UCLK=UPLL/2
UCLK = (rCLKDIVN&8)?(UPLL>>1):UPLL;
}
void UsbdMain(void)
{
//int i;
//U8 tmp1;
//U8 oldTmp1=0xff;
//ChangeUPllValue(0x38,2,1); // UCLK=96Mhz
// ChangeUPllValue(0x38,2,2); // UCLK=48Mhz
InitDescriptorTable();
//ResetUsbd();
rGPGUP |= 1<<9; //disable pull-up
rGPGCON &= ~(3<<18);
Delay(2000);
rGPGDAT |= 1<<9; //high
rGPGCON |= 1<<18; //output
ConfigUsbd();
//DetectVbus(); //not used in S3C2400X
PrepareEp1Fifo();
#if 0
while(1)
{
if(DbgPrintfLoop())continue;
Delay(5000);
if((i++%2)==0)Led_Display(0x8);
else Led_Display(0x0);
}
#endif
}
{
ReconfigUsbd();
/*
pISR_USBD =(unsigned)IsrUsbd;
ClearPending(BIT_USBD);
rINTMSK&=~(BIT_USBD);
*/
rINTMSK&=~(BIT_USBD);
}