求问VHDL中自带了除法运算的吗？

[shaoqikai1234]

LZ是新手，玩各位牛人解答的详细一点

[哈皮歪詩]

Division is different from addition and multiplication in that there is no good way to do division in hardware. Unlike addition or multiplication, where there are solutions like CLA (Carrier look ahead), CSA (Carry Save Adder) etc, it is always a hassle to do division. For many synthesizers, they are smart enough to extract adder and multiplier and map them to the default library (It is especially true for FPGA, which has built-in adder and multipliers), but they might frown upon division. So it is ok to do something like "a <= b * c;" in your VHDL code, but for division, it is better to do it explicitly with a library mapping.

[jnwsh]

vhdl是一种硬件描述语言，怎么会带除法器。除法器是综合或者仿真时相应library支持的，这个lib也可以自己建