求帮助,高手解决verilog设计数字滤波器时滤波器的系数是怎么得到的?
module fir8(out,in,clk,rst);
parameter size_in = 8;
parameter size_out = 2*size_in+1;
//这下面的滤波器系数是怎么得到的?有什么作用,设计高通,带通,带阻滤波器时,是要确定这儿的系数吗?
parameter h0 = 8'd7;
parameter h1 = 8'd17;
parameter h2 = 8'd32;
parameter h3 = 8'd46;
parameter h4 = 8'd52;
parameter h5 = 8'd46;
parameter h6 = 8'd32;
parameter h7 = 8'd17;
parameter h8 = 8'd7;
output [size_out-1:0] out;
input [size_in-1:0] in;
input clk,rst;
reg [size_in-1:0] samples1;
reg [size_in-1:0] samples2;
reg [size_in-1:0] samples3;
reg [size_in-1:0] samples4;
reg [size_in-1:0] samples5;
reg [size_in-1:0] samples6;
reg [size_in-1:0] samples7;
reg [size_in-1:0] samples8;
assign out = h0*in+h1*samples1+h2*samples2+h3*samples3+h4*samples4+h5*samples5+h6*samples6+h7*samples7+h8*samples8;
always@ (posedge clk or negedge rst)
if(rst==0)
beginsamples1<=0;
samples2<=0;
samples3<=0;
samples4<=0;
samples5<=0;
samples6<=0;
samples7<=0;
samples8<=0;
endelsebeginsamples1<=in;
samples2<=samples1;
samples3<=samples2;
samples4<=samples3;
samples5<=samples4;
samples6<=samples5;
samples7<=samples6;
samples8<=samples7 ;
endendmodule