求帮助，高手解决verilog设计数字滤波器时滤波器的系数是怎么得到的？

2011-04-18 11:20:13 542 阅读 AI 写同款 · GEO 优化AI 选题数据监测一键分发 ›

module fir8(out,in,clk,rst);
parameter size_in = 8;
parameter size_out = 2*size_in+1;
//这下面的滤波器系数是怎么得到的？有什么作用，设计高通，带通，带阻滤波器时，是要确定这儿的系数吗？
parameter h0 = 8'd7;
parameter h1 = 8'd17;
parameter h2 = 8'd32;
parameter h3 = 8'd46;
parameter h4 = 8'd52;
parameter h5 = 8'd46;
parameter h6 = 8'd32;
parameter h7 = 8'd17;
parameter h8 = 8'd7;
output [size_out-1:0] out;
input [size_in-1:0] in;
input clk,rst;
reg [size_in-1:0] samples1;
reg [size_in-1:0] samples2;
reg [size_in-1:0] samples3;
reg [size_in-1:0] samples4;
reg [size_in-1:0] samples5;
reg [size_in-1:0] samples6;
reg [size_in-1:0] samples7;
reg [size_in-1:0] samples8;
assign out = h0*in+h1*samples1+h2*samples2+h3*samples3+h4*samples4+h5*samples5+h6*samples6+h7*samples7+h8*samples8;
always@ (posedge clk or negedge rst)
if(rst==0)
beginsamples1<=0;
samples2<=0;
samples3<=0;
samples4<=0;
samples5<=0;
samples6<=0;
samples7<=0;
samples8<=0;
endelsebeginsamples1<=in;
samples2<=samples1;
samples3<=samples2;
samples4<=samples3;
samples5<=samples4;
samples6<=samples5;
samples7<=samples6;
samples8<=samples7 ;
endendmodule

...全文

FPGA实现FIR滤波器 1、FIR滤波器总体设计本设计是基于FPGA实现一个8阶的FIR数字低通滤波器。本次设计首先利用MATLAB中的FDAtool工具设计出一个采样频率为5KHZ、截止频率为1KHZ的FIR低通滤波器，通过FDAtool导出8点系数，然后将系数进行放大、取整，以便于在FPGA中使用，最后通过QuartusII进行Verilog语言编写滤波器算法，然后通过Modesim仿真结果和MATLAB仿真结果阅读详情

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切换为时间正序

jiayinta 2011-04-21

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[Quote=引用 7 楼 hahahaha_hax4 的回复:]
引用 6 楼 jiayinta 的回复:

module iir_cascsde_2(clk,rst,in,out);
input clk;
input rst;
input [15:0] in;
output [15:0] out;
wire [15:0] y1_out;

parameter a1_1 = 36504;
parameter a1_2 = -23396;
p……
[/Quote]
为什么这16位就相对次要些了？而高16位就重要些？

whybb101 2011-04-21

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数字滤波器的系数是用MATLAB算好了用的

哈皮歪詩 2011-04-21

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[Quote=引用 6 楼 jiayinta 的回复:]

module iir_cascsde_2(clk,rst,in,out);
input clk;
input rst;
input [15:0] in;
output [15:0] out;
wire [15:0] y1_out;

parameter a1_1 = 36504;
parameter a1_2 = -23396;
parameter b1_1 = 0;
par……
[/Quote]

You drop the lower 16 bits since they are less significant.

jiayinta 2011-04-20

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module iir_cascsde_2(clk,rst,in,out);
input clk;
input rst;
input [15:0] in;
output [15:0] out;
wire [15:0] y1_out;

parameter a1_1 = 36504;
parameter a1_2 = -23396;
parameter b1_1 = 0;
parameter b1_2 = 32768;

parameter a2_1 = 0;
parameter a2_2 = 58832;
parameter b2_1 = 32768;
parameter b2_2 = 36054;

sub2 sub2_1(.clk(clk),.rst(rst),.a1(a1_1),.a2(a1_2),.b1(b1_1),.b2(b1_2),.x_in(in),.y_out(y1_out));
sub2 sub2_2(.clk(clk),.rst(rst),.a1(a2_1),.a2(a2_2),.b1(b2_1),.b2(b2_2),.x_in(y1_out),.y_out(out));

endmodule

module sub2(clk,rst,a1,a2,b1,b2,x_in,y_out);
input clk;
input rst;
input [15:0] a1;
input [15:0] a2;
input [15:0] b1;
input [15:0] b2;
input [15:0] x_in;
output [15:0] y_out;

reg [47:0] x_temp;
reg [47:0] y_temp;
wire [31:0] x_t;
wire [31:0] y_t;

always @ (posedge clk) begin
if(!rst) begin
x_temp <= 0;
y_temp <= 0;
end
else
begin
x_temp[47:0] <= {x_temp[31:0],x_in};
y_temp[47:0] <= {y_temp[31:0],x_t[31:16]};
end
end
assign x_t = rst ? x_temp[47:32]*a2 + x_temp[31:16]*a1 + x_temp[15:0] : 0;
assign y_t = rst ? y_temp[47:32]*b2 + y_temp[31:16]*b1 + y_temp[15:0] : 0;

assign y_out[15:0] = y_t[31:16];
endmodule
这里的y_out为什么取得y_t的高16位，那低16位没有用吗？

哈皮歪詩 2011-04-19

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[Quote=引用 4 楼 jiayinta 的回复:]

呵呵，我现在明白了，可是我用matlab设计得到的系数是浮点数，还要弄成整数吗？
[/Quote]

Yes, you have to convert float point to integer

jiayinta 2011-04-18

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呵呵，我现在明白了，可是我用matlab设计得到的系数是浮点数，还要弄成整数吗？

哈皮歪詩 2011-04-18

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[Quote=引用 2 楼 jiayinta 的回复:]

这是低通滤波器，那么是通过什么来实现低通而不是高通？
[/Quote]

If as you said, it is a LPF, then that's because these coefficients are designed such that mathematically high freq components will be damped after convolution with these coefficients. That's why you have to find your answer by inputting these coefficients into Matlab or any other math tools.

jiayinta 2011-04-18

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这是低通滤波器，那么是通过什么来实现低通而不是高通？

哈皮歪詩 2011-04-18

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Those coefficients have nothing to do with the verilog .Verilog is just a way to implement the filter. You should ask your system engineer, or use Matlab to see the filter spectrum to determine the characteristics of your filter.

As for the implementation itself, the best way to implement a FIR is transposed structure. (Transposed structure is scalable, which could avoid the big tree adder you have in your above code. Please Google for more detail.)

求帮助，高手解决verilog设计数字滤波器时滤波器的系数是怎么得到的？

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