macrocell 不够用怎么办？

[ivorstar]

verilog写了个小程序，发现macrocell需要6XX，找了几个cpld平台好像最大只能支持到512，有没有支持更多的？还是只能选择fpga？

或者能不能优化程序？


`timescale 1ns / 1ps

module tmvp(a, b, c);
input [62:0] a;
input [31:0] b;
output [31:0] c;

tmvp_32 m1 (a, b, c);

endmodule

module tmvp_32(a, b, c);
input [62:0] a;
input [31:0] b;
output [31:0] c;

wire [30:0] t01;
wire [30:15] t12;
wire [15:0] b01, p0, p1, p2;

//calc T0+T1
assign t01 = a[30:0] ^ a[46:16];

//calc the first column of T1+T2, t12[-1:-n] = t01[n:1]
assign t12 = a[46:31] ^ a[62:47];
assign b01 = b[15:0] ^ b[31:16];

tmvp_16 mul_1 (t01, b[31:16], p0),
mul_2 ({t12, t01[30:16]}, b[15:0], p1),
mul_3 (a[46:16], b01, p2);

assign c[31:16] = (p1 & ~p2) | (~p1 & p2);
assign c[15:0] = (p0 & ~p2) | (~p0 & p2);
endmodule


module tmvp_16(a, b, c);
input [30:0] a;
input [15:0] b;
output [15:0] c;

wire [14:0] t01;
wire [14:7] t12;
wire [7:0] b01, p0, p1, p2;

//calc T0+T1
assign t01 = a[14:0] ^ a[22:8];

//calc the first column of T1+T2, t12[-1:-n] = t01[n:1]
assign t12 = a[14:7] ^ a[30:23];
assign b01 = b[7:0] ^ b[15:8];

tmvp_8 mul_1 (t01, b[15:8], p0),
mul_2 ({t12, t01[14:8]}, b[7:0], p1),
mul_3 (a[22:8], b01, p2);

assign c[15:8] = p1 ^ p2;
assign c[7:0] = p0 ^ p2;
endmodule


module tmvp_8(a, b, c);
input [14:0] a;
input [7:0] b;
output [7:0] c;

wire [6:0] t01;
wire [6:3] t12;
wire [3:0] b01, p0, p1, p2;

//calc T0+T1
assign t01 = a[6:0] ^ a[10:4];

//calc the first column of T1+T2, t12[-1:-n] = t01[n:1]
assign t12 = a[10:7] ^ a[14:11];
assign b01 = b[3:0] ^ b[7:4];

tmvp_4 mul_1 (t01, b[7:4], p0),
mul_2 ({t12, t01[6:4]}, b[3:0], p1),
mul_3 (a[10:4], b01, p2);

assign c[7:4] = p1 ^ p2;
assign c[3:0] = p0 ^ p2;
endmodule

module tmvp_4(a, b, c);
input [6:0] a;
input [3:0] b;
output [3:0] c;

wire [2:0] t01;
wire [2:1] t12;
wire [1:0] b01, p0, p1, p2;

//calc T0+T1
assign t01 = a[2:0] ^ a[4:2];

//calc the first column of T1+T2, t12[-1:-n] = t01[n:1]
assign t12 = a[4:3] ^ a[6:5];
assign b01 = b[1:0] ^ b[3:2];

tmvp_2 mul_1 (t01, b[3:2], p0),
mul_2 ({t12, t01[2]}, b[1:0], p1),
mul_3 (a[4:2], b01, p2);

assign c[3:2] = p1 ^ p2;
assign c[1:0] = p0 ^ p2;
endmodule

module tmvp_2(a, b, c);
input [2:0] a;
input [1:0] b;
output [1:0] c;

wire t01;
wire t12, p0, p1, p2;

//calc T0+T1
assign t01 = a[0] ^ a[1];

//calc the first column of T1+T2, t12[-1:-n] = t01[n:1]
assign t12 = a[1] ^ a[2];
assign b01 = b[0] ^ b[1];

//calc p0, p1, p2
and (p0, t01, b[1]),
(p1, t12, b[0]),
(p2, b01, a[1]);

assign c[0] = p0 ^ p2;
assign c[1] = p1 ^ p2;
endmodule

[net_friends]

换FPGA吧，容量大

[jnwsh]

cpld也有容量大的，实在不行，考虑fpga吧