你可能理解成我说的RAM是片外RAM了,我说的实际上就是FPGA片内RAM。硬件上的FIFO强调的是读写同时进行,从而压缩延迟,而你说的读写分时间进行的用法实际上就是在操作RAM。
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谢谢您的说明。我们之前有一个产品把FIFO是建立在FPGA block RAM上,通过DMA把FIFO拷贝到ARM CPU RAM, 我不知道DMA是否每次都拷贝固定长度数据。期望的工作模式是一边写一边读出来往ARM CPU RAM传,但是写入数据的速度和数量是不定的。有可能100us只写几个字节,也可能超出FIFO容量,要分多次写入和传输,这样的需求大概要怎么实现呢?
这个描述的并不清晰,怎么还要用到DMA直连FIFO呢。这不是直接把FIFO当成RAM在用了么。据我所知不管是读还是写存储器的DMA,都需要先有源数据的确知大小才可以啊。如果要用读写指针的位置来算数据大小这不是画蛇添足么。
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FIFO是FPGA上的内存,通过DMA拷贝到CPU RAM.下面这一段是来自Virtex-6 Family Overview
FIFO Controller
The built-in FIFO controller for single-clock (synchronous) or dual-clock (asynchronous or multirate) operation increments
the internal addresses and provides four handshaking flags: full, empty, almost full, and almost empty. The almost full and
almost empty flags are freely programmable. Similar to the block RAM, the FIFO width and depth are programmable, but the
write and read ports always have identical width. First-word fall-through mode presents the first-written word on the data
output even before the first read operation. After the first word has been read, there is no difference between this mode and
the standard mode.