vhdl uart设计问题

gftomren 2012-08-01 08:52:50

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity uart is
port(
clk_in,clk_in_100hz : in std_logic;
rxd_in: in std_logic;
rxd_out:out std_logic_vector(7 downto 0)
);
end uart;

architecture a of uart is
type state is(idle,check,rec);
signal check_ck,rec_ck,rec_re,rec_cc,ok:std_logic;
signal check_re: std_logic_vector(1 downto 0):="00";
signal recv,recv_sig : std_logic_vector(7 downto 0):="00000000";
signal rxd_ck,rxd_ck_sig : std_logic_vector(3 downto 0):="0000";
signal sta : state;
begin

process(sta,rxd_in,check_re,rec_re)
begin
case sta is
when idle=>
recv_sig<="00000000";
if rxd_in='0' then
sta<=check;
else
sta<=idle;
end if;
when check=>
check_ck<='1';
case check_re is
when "01"=>
check_ck<='0';
sta<=rec;
when "10"=>
check_ck<='0';
sta<=idle;
when others=> null;
end case;
when rec=>
rec_ck<='1';
if rec_re='1' then
sta<=idle;
rec_ck<='0';
elsif ok='1' then
rxd_out<=recv_sig;
sta<=idle;
rec_ck<='0';
end if;
end case;
end process;

process(clk_in,check_ck,rec_ck,clk_in_100hz,rec_cc)
variable rxd_ck_st : integer range 0 to 4:=0;
variable rec_st : integer range 0 to 8:=0;
begin
if check_ck='1' then
if clk_in'event and clk_in='1' then
if rxd_ck_st<=4 then
rxd_ck_st:=rxd_ck_st+1;
rxd_ck<=rxd_in & rxd_ck_sig(3 downto 1);
else
if rxd_ck_sig="0000" then
check_re<="01";
rxd_ck_st:=0;
else
check_re<="10";
rxd_ck_st:=0;
end if;
end if;
end if;
end if;
if rec_ck='1' then
if clk_in_100hz'event and clk_in_100hz='1' then
if rec_st<=8 then
rec_st:=rec_st+1;
recv<=rxd_in & recv_sig(7 downto 1);
else
rec_cc<=rxd_in;
if rec_cc='1' then
ok<='1';
else
rec_re<='1';
end if;
end if;
end if;
end if;
end process;
end a;

请问UART的写法这样子的思考方法对不对?，
一个状态机先等待初始位元当变成0的时候 (9600bps) 用一个除频到25Hz的取样4次(1/9600大约100Hz)，
然後当4次都是低电位就是初始位元，
状态机进到接收资料用100Hz取8个位元，之後状态机进到检查停止位元是不是高电位如果是就输出~
写出来的像上面那个样子clk_in是25hz另一个是100hz，
没有实体可以测试，请各位帮我看看
谢谢

...全文