register file是什么？和普通的寄存器有什么区别？

ctbt201 2012-11-08 01:59:30

在CEVA DSP里面，哪位大侠请指教，非常感谢！
另外，为什么寄存器名字叫accumulator呢？

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ctbt201 2012-11-08

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另外@of123,您用这个美女图像，搞得我都无法专心思考问题了

ctbt201 2012-11-08

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非常感谢，寄存器堆，应该就是传统寄存器里面的通用寄存器吧? 寄存器堆里面所有的寄存器都叫accumulator，以前X86里面8个通用寄存器里面也只有一个累加器。

of123 2012-11-08

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register file 通常译为寄存器堆。 accumulator 是累加器，寄存器之一。

Register File is a large structure in the contemporary microprocessors and its access time and energy dissipation is significant compared to other components. Number of registers used in current processors is usually a bottleneck in the processors since the access time of the register file constrain

在行为VHDL中（使用3个并发进程）描述图1所示的MIPS寄存器文件，该文件通过以下接口支持3操作数算术运算： • Generics: - Register file size/depth (reg_file_depth with default value of 23 registers) - Register file width (reg_file_width with default value of 32 bits) • Inputs: - Clock (clk -> 1 bit) - Asynchronous reset (rst -> 1 bit) - Register write enable (RegWrite -> 1 bit) 1 -> enable writing to register file, 0 -> disable writing to register file - Read Address for first (read) operand (RA1 -> [log2 (reg_file_depth)] bits) - Read Address for second (read) operand (RA2 -> [log2 (reg_file_depth)] bits) - Write Address for third (write) operand (WA -> [log2 (reg_file_depth)] bits) - Write Data for third (write) operand (WD -> reg_file_width bits) • Outputs: - Read Data for first (read) operand (RD1 -> reg_file_width bits) - Read Data for second (read) operand (RD2 -> reg_file_width bits) • In Vivado - Create a blank project - Add design and simulation source files - Run behavioral simulation - Your waveform configuration should be identical to the provided waveform snapshot, see Figure 2. • In your design: - Guard against address-spilling (address-overflow) where addresses could go out of range, e.g., exceeding the register file size/depth. - Guard against unintentional writes to register zero ($0), i.e., $0 is read-only and has always the value 0.

gen_apb_file是一种开源的寄存器文件解决方案,包括中心化的寄存器描述文件(Excel格式)和相应的寄存器文件生成脚本,能够快速生成寄存器硬件模块、ralf模型、c语言头文件。主要有以下特性: 支持APB接口类型 寄存器位宽可配支持25种寄存器存取类型[2](见下表) 可生成verilog 可生成ralf 可生成c header 支持多个模块

杭电计组实验4-寄存器堆设计实验.doc

File Register ADE9153A

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