VS无法设置默认的Code Page(encoding)?

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问题描述:

我希望达到的一种状态是,每次在project里新建一个cpp文件,然后敲代码,然后Ctrl+S保存,希望每次默认都能保存成utf-8的。
但是每次这样操作,保存的都是gb2312的。
必需打开File>Advanced Save Options...才能设置。

OS:win7 64bit 中文版
VS:2012 英文版

目前看到的解决办法:

1> 将操作系统语言改成英语,因为VS是根据操作系统的code page进行设置的。
2> 自己写个程序,遍历源代码文件夹,将所有文件转换encoding。

感觉这两种方法都很不方便,尤其是如果忘记了,就会造成源代码的encoding不一致。
有认识微软开发VS的人吗?能给他们提意见吗?这个功能很多人都期待,但是到目前都不知道如何解决。
...全文

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National_Semiconductor的一款网络芯片的技术手册。1.0 Pin Descriptions m 9 1.1 Serial Management Interface 9 1.2 MAC Data Interface .9 1.3 Clock Interface 11 1. 4 LED Interface 1.5 Reset and Power down 12 1.6 Strap Options 12 1.7 10 Mb/s and 100 Mb/s PMD Interface 14 1.8 Special Connections 14 1. 9 Power Supply Pi 14 1. 10 Package Pin AsSi 15 2.0 Configuration 16 2. 1 Auto-Negotiation g 16 2.1.1 Auto-Negotiation Pin Control 16 2.1.2 Auto-Negotiation Register Control 16 2.1.3 Auto-Negotiation Parallel Detection 2. 1. 4 Auto-Negotiation Restart 2.1.5 Enabling Auto-Negotiation via Software 17 2.1.6 Auto-Negotiation Complete Time 17 2.2 Auto-MDIX 2. 3 PHY Address 18 2.3.1 Mll Isolate mode 2.4 LED Interface 19 2.4.1LED 19 2.4.2 LED Direct Control 2.5 Half Duplex VS Full Duplex 20 2.6 Internal Loopback 20 2.7 BIST 20 3.0 Functional Description .I.I... 21 3.1 Mll Interface 3.1.1 Nibble-wide mll data Interface 21 3.1.2 Collision detect 3.1.3 Carrier Sense 21 3.2 Reduced mll Interface 3.3 10 Mb Serial Network Interface(SNI) .22 3. 4 802.3u Mll Serial Management Interface 3.4.1 Serial Management Register Access 3.4.2 Serial Management Access protocol 22 3.4.3 Serial Management Preamble Suppression 4.0 Architecture 24 4.1100BASE-TX TRANSMITTER .24 4.1. 1 Code-group Encoding and Injection 26 4.1.2 Scrambler 26 4.1 3 Nrz to nrzi Encoder 26 4.1. 4 Binary to MLT-3 Convertor 26 4.2100 BASE-T×RECEⅣVER 26 4.2.1 Analog Front Et 26 4.2.2 Digital Signal Processor 26 4.2.2.1 Digital Adaptive Equalization and gain Control 28 4.2.2.2 Base Line Wander Compensation 4.2.3 Signal detect 4.2.4 MLT-3 to nrzi Decoder 4,25 nrz to nrz 4.2.6 Serial to parallel 4.2.7 Descrambler 4.2.8 Code-group Alignment 4.29 4B/5B Decoder 4.2. 10 100BASE-TX Link Integrity Monitor ..30 42. 11 Bad ssD Detection .30 www.national.com Oo寸∞∞∞ 4.3 10BASE-T TRANSCEIVER MODULE 30 4.3.1 Operational Modes 30 4.3.2 Smart squelch 31 4.3.3 Collision Detection and sQE 4.3.4 Carrier Sense 31 4.3.5 Normal Link Pulse detection/Generation 4.3.6 Jabber function …32 4.3. 7 Automatic Link Polarity detection and correction .....32 4.3.8 Transmit and Receive Filtering ...32 4.3.9 Transmitter 4.3.10 Receiver 5.0 Design Guidelines 33 5. 1 TPI Network circuit ....33 5.2 ESD Protection 34 5.3 Clock In(X1) Requirements 34 5. 4 Power feedback circu 35 5.5 Power Down/Interrupt 35 5.5.1 Power down control mode ....35 5.5.2 Interrupt Mechanisms 5.6 Energy Detect Mode 36 6.0 Reset Operation..∴.∴∴∴.37 6.1 Hardware reset 6.2 Software reset 7.0 Register Block ,,,,,,,,,38 7. 1 Register definition 7.1.1 Basic Mode Control Register(BMCR) 7.1.2 Basic Mode Status Register(BMSR) 44 7.1.3 PHY Identifier Register #1 (PHYIDR1) 45 7.1. 4 PHY Identifier Register #2(PHYIDR2 ..45 7.1.5 Auto-Negotiation Advertisement Register(ANAR) .......45 7.1.6 Auto-Negotiation Link Partner Ability Register(ANLPAR) (BASE Page) 7.1.7 Auto-Negotiation Link Partner Ability Register(ANLPAR)(Next Page) 7.1.8 Auto-Negotiate Expansion Register (ANER) 7.1.9 Auto-Negotiation Next Page Transmit Register(ANNPTR) 7.2 EXtended Registers 50 7.2.1 PHY Status Register(PHYSTS 7.2.2 Mll Interrupt Control Register(MICR 52 7.2.3 MIl Interrupt Status and Misc. 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DP83848C Functional Block Diagram..... Figure 2. PHYAD Strapping Example 18 Figure 3. AN Strapping and LED Loading Example 19 Figure 4. Typical MDC/MDIO Read Operation ......23 Figure 5. Typical MDC/MDIO Write Operation 23 Figure 6. 100BASE-TX Transmit Block Diagram ,,,,,,.,,.24 Figure 7. 100BASE-TX Receive Block Diagram 27 Figure 8. EIA/TIA Attenuation Vs Frequency for 0, 50, 100, 130&amp;150 meters of CAt 5 cable...... 28 Figure 9. 100BASE-TX BLW Event ........ Figure 10. 10BASE-T Twisted Pair Smart Squelch Operation 31 Figure 11 10/100 Mb/s Twisted Pair Interface...,.......... 33 Figure 12. Crystal Oscillator Circuit 34 Figure 13. Power Feeback Connection 35 www.national.com List of tables Table 1. Auto-Negotiation Modes .16 Table 2. PHY Address Mapping Table 3. lEd Mode select 19 Table 4. Supported packet sizes at +/-50ppm +/-100ppm for each clock Table 5. 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PD that accept data synchronous to the 50 MHz reference clock SNI TRANSMIT DATA: Transmit data sNi input pin TXd 0, that accept data synchronous to the TX CLK (10 MHz in 10 Mb/s sni mode) www.national.com Oo寸∞∞∞ Signal name Type Pin #i Description RX CLK 38 MI RECEE CLOCK: Provides the 25 mhz recovered receive clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode Unused in rmll mode the device uses the xl reference clock in put as the 50 MHz reference for both transmit and receive SNI RECEIVE CLOCK: Provides the 10 MHz recovered receive clocks for 10 Mb/s sni mode RXD∨ S.O. PD MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the corresponding RXD[3: 0]. MIl mode by de fault with internal pulldown RMII Synchronous Receive Data Valid: This signal provides the RMII Receive Data valid indication independent of carrier sense This pin is not used in SNI mode RX ER S.O. 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