at91sam9g45的WINCE系统起不来
大家好!我是嵌入式新手,在调试AT91SAM9G45时碰到系统起不来问题,只出来WINCE log,然后LCD黑下去,打印I2C erro
INFO : Low Level Init : OK
INFO : DDRam init : OK
Init Nand flash
Load CE-BOOT from Flash to DDRAM
Starting eboot ...
Debug serial initialized ........OK
Microsoft Windows CE Bootloader Common Library Version 1.4 Built Jul 31 2013 19:59:50
Microsoft Windows CE 6.0 Ethernet Bootloader for the AT91SAM926xEK board
Adaptation performed by ADENEO (c) 2007
Debug serial initialized ........OK
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--- Configuring Chip Select 3 ---
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--- Desired timings ---
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dwNWE_SETUP 16
dwNCS_WR_SETUP 0
dwNRD_SETUP 16
dwNCS_RD_SETUP 0
dwNWE_PULSE 32
dwNCS_WR_PULSE 32
dwNRD_PULSE 32
dwNCS_RD_PULSE 32
dwNRD_CYCLE 56
dwNWE_CYCLE 56
dwClockPeriod_ns 8
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--- Real timings ---
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dwNWE_SETUP 16
dwNCS_WR_SETUP 0
dwNRD_SETUP 16
dwNCS_RD_SETUP 0
dwNWE_PULSE 32
dwNCS_WR_PULSE 32
dwNRD_PULSE 32
dwNCS_RD_PULSE 32
dwNRD_CYCLE 56
dwNWE_CYCLE 56
Found Smug (0xec)- K9F2G08U0A (0xda)
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--- Configuring Chip Select 3 ---
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--- Desired timings ---
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dwNWE_SETUP 16
dwNCS_WR_SETUP 0
dwNRD_SETUP 16
dwNCS_RD_SETUP 0
dwNWE_PULSE 32
dwNCS_WR_PULSE 32
dwNRD_PULSE 32
dwNCS_RD_PULSE 32
dwNRD_CYCLE 56
dwNWE_CYCLE 56
dwClockPeriod_ns 8
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--- Real timings ---
---------------------------------------
dwNWE_SETUP 16
dwNCS_WR_SETUP 0
dwNRD_SETUP 16
dwNCS_RD_SETUP 0
dwNWE_PULSE 32
dwNCS_WR_PULSE 32
dwNRD_PULSE 32
dwNCS_RD_PULSE 32
dwNRD_CYCLE 56
dwNWE_CYCLE 56
Using Software ECC
FMD_DirectRead lasted 1 ms for 0x62 bytes (timer granularity is 400)
WARNING : LoadEBootCFG: No valid Eboot configuration found.
INFO : Loading default bootloader settings
Press [ENTER] to launch image stored in flash or [SPACE] to cancel.
Initiating image launch in 0 seconds
System ready!
Preparing for download...
dwFlashLogicalAddress: e0200000
OK
FMD_DirectRead lasted 9994 ms for 0x2000000 bytes (timer granularity is 400)
Launching windows CE image by jumping at address 0x70195000Windows CE Kernel for ARM (Thumb Enabled) Built on Sep 30 2007 at 22:37:06
Windows CE Firmware Init
BSP 1.4.0 for the AT91SAM9G45M10EK board (built Jul 31 2013)
Adaptation performed by ADENEO (c) 2005
+OALIntrInit
+SOCPioIntrInit()
-SOCPioIntrInit()
-OALIntrInit(rc = 1)
Initialize driver globals Zeros area...
pDrvGlobalArea 0x80193000 size 0x800 (0x80193800 -0x80193000)
Initialize driver globals Zeros area...done
-------------------
|PLLA : 399974400 Hz|
--------------------
OALTimerInit
+OALTimerInit
Test : 0x208c
g_oalTimer.msecPerSysTick : 0x1
g_oalTimer.countsPerMSec : 0x208c
g_oalTimer.countsMargin : 0x0
g_oalTimer.maxPeriodMSec : 0x7c
g_oalTimer.countsPerSysTick : 0x208c
g_oalTimer.actualMSecPerSysTick : 0x1
g_oalTimer.actualCountsPerSysTick : 0x208c
g_oalTimer.curCounts : 0x0
-OALTimerInit
reset : Watchdog Reset
pDrvGlobalArea->bEboot == TRUE. Forcing Clean Object store
+OEMPowerManagerInit
-OEMPowerManagerInit
OALKitlStart
Firmware Init Done.
+OEMInitWatchDogTimer
AT91SAM926x_DispWatchDog 3fff2fff!
AT91SAM926x_SetWatchDogConfiguration 20000 => 5120
Clipping The Watchdog period to the maximum : 0xFFF (15996 ms)
-OEMInitWatchDogTimer (result = 15996)
+OALIoCtlHalInitRTC(...)
setrealtime 3062694400
-OALIoCtlHalInitRTC(rc = 1)
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--- Configuring Chip Select 3 ---
---------------------------------------
--- Desired timings ---
---------------------------------------
dwNWE_SETUP 16
dwNCS_WR_SETUP 0
dwNRD_SETUP 16
dwNCS_RD_SETUP 0
dwNWE_PULSE 32
dwNCS_WR_PULSE 32
dwNRD_PULSE 32
dwNCS_RD_PULSE 32
dwNRD_CYCLE 56
dwNWE_CYCLE 56
dwClockPeriod_ns 8
---------------------------------------
--- Real timings ---
---------------------------------------
dwNWE_SETUP 16
dwNCS_WR_SETUP 0
dwNRD_SETUP 16
dwNCS_RD_SETUP 0
dwNWE_PULSE 32
dwNCS_WR_PULSE 32
dwNRD_PULSE 32
dwNCS_RD_PULSE 32
dwNRD_CYCLE 56
dwNWE_CYCLE 56
Found Smug (0xec)- K9F2G08U0A (0xda)
---------------------------------------
--- Configuring Chip Select 3 ---
---------------------------------------
--- Desired timings ---
---------------------------------------
dwNWE_SETUP 16
dwNCS_WR_SETUP 0
dwNRD_SETUP 16
dwNCS_RD_SETUP 0
dwNWE_PULSE 32
dwNCS_WR_PULSE 32
dwNRD_PULSE 32
dwNCS_RD_PULSE 32
dwNRD_CYCLE 56
dwNWE_CYCLE 56
dwClockPeriod_ns 8
---------------------------------------
--- Real timings ---
---------------------------------------
dwNWE_SETUP 16
dwNCS_WR_SETUP 0
dwNRD_SETUP 16
dwNCS_RD_SETUP 0
dwNWE_PULSE 32
dwNCS_WR_PULSE 32
dwNRD_PULSE 32
dwNCS_RD_PULSE 32
dwNRD_CYCLE 56
dwNWE_CYCLE 56
Using Software ECC
SPIDriver - DLL_PROCESS_ATTACH
+CUSBHSFN::Init()
UDPHS IT: Thread started-CUSBHSFN::Init()
+CUSBHSFN::InitEndpoint(0)
-CUSBHSFN::InitEndpoint(0)
IOControl IOCTL_BUS_GET_POWER_STATE(D0)
PWM Driver: DLL_PROCESS_ATTACH
PLLA Clock is 399974400 Hz
I2C Error: AT91C_TWI_NACK
I2C Error: AT91C_TWI_NACK
I2C Error: AT91C_TWI_NACK
I2C Error: AT91C_TWI_NACK
I2C Error: AT91C_TWI_NACK
I2C Error: AT91C_TWI_NACK
I2C Error: AT91C_TWI_NACK
I2C Error: AT91C_TWI_NACK
I2C Error: AT91C_TWI_NACK
I2C Error: AT91C_TWI_NACK
I2C Error: AT91C_TWI_NACK
I2C Error: AT91C_TWI_NACK
Display mode #0, 800x480x16bpp @ 0hz
Frame buffer is Uncached
Config2DEngine
cable attached