硬件设计
帮忙看一下verilog错误原因，多谢！
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我也要 关注 + 加入社区#module ls1(clk,rst_m,fm);
input clk;//时钟信号50MHZ
input rst_m;//复位，低电平有效
output fm;//蜂鸣器 0--响，1--不响
reg(5:0) cnt;
always @(posedge clk or negedge rst_m)
if(rst_m) cnt <=6'd0;
else if(cnt<49) cnt=cnt+1'b1;
else cat=6'd0;
assign fm=(cnt <= 6'd24)?1'b0:1'b1;
endmodule
这是程序 编译结果有错误
Warning (20028): Parallel compilation is not licensed and has been disabled
Error (10170): Verilog HDL syntax error at ls1.v(1) near text "#"; expecting a description
Error: Quartus II 32-bit Hierarchy Elaboration was unsuccessful. 1 error, 1 warning
Error: Peak virtual memory: 332 megabytes
Error: Processing ended: Sun Dec 29 12:26:33 2013
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
input clk;//时钟信号50MHZ
input rst_m;//复位，低电平有效
output fm;//蜂鸣器 0--响，1--不响
reg(5:0) cnt;
always @(posedge clk or negedge rst_m)
if(rst_m) cnt <=6'd0;
else if(cnt<49) cnt=cnt+1'b1;
else cat=6'd0;
assign fm=(cnt <= 6'd24)?1'b0:1'b1;
endmodule
这是程序 编译结果有错误
Warning (20028): Parallel compilation is not licensed and has been disabled
Error (10170): Verilog HDL syntax error at ls1.v(1) near text "#"; expecting a description
Error: Quartus II 32-bit Hierarchy Elaboration was unsuccessful. 1 error, 1 warning
Error: Peak virtual memory: 332 megabytes
Error: Processing ended: Sun Dec 29 12:26:33 2013
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
...全文
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verilog编译错误及warning汇总[文].pdf
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