帮忙看一下verilog错误原因，多谢！

[lee887]

#module ls1(clk,rst_m,fm);

input clk;//时钟信号50MHZ
input rst_m;//复位，低电平有效
output fm;//蜂鸣器 0--响，1--不响

reg(5:0) cnt;

always @(posedge clk or negedge rst_m)
if(rst_m) cnt <=6'd0;
else if(cnt<49) cnt=cnt+1'b1;
else cat=6'd0;

assign fm=(cnt <= 6'd24)?1'b0:1'b1;

endmodule

这是程序 编译结果有错误
Warning (20028): Parallel compilation is not licensed and has been disabled
Error (10170): Verilog HDL syntax error at ls1.v(1) near text "#"; expecting a description
Error: Quartus II 32-bit Hierarchy Elaboration was unsuccessful. 1 error, 1 warning
Error: Peak virtual memory: 332 megabytes
Error: Processing ended: Sun Dec 29 12:26:33 2013
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01

[SLZ2011]

第一行那个#不要

[lee887]

引用 1 楼 SLZ2011 的回复:

第一行那个#不要

去掉# 结果变成了这样： Warning (20028): Parallel compilation is not licensed and has been disabled Error (10170): Verilog HDL syntax error at ls1.v(7) near text "("; expecting an identifier Error (10112): Ignored design unit "ls1" at ls1.v(1) due to previous errors Info (12021): Found 0 design units, including 0 entities, in source file ls1.v Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 2 errors, 1 warning Error: Peak virtual memory: 332 megabytes Error: Processing ended: Mon Dec 30 08:02:38 2013 Error: Elapsed time: 00:00:08 Error: Total CPU time (on all processors): 00:00:01

[falloutmx]

module ls1(clk,rst_m,fm);

input clk;//时钟信号50MHZ
input rst_m;//复位，低电平有效
output fm;//蜂鸣器 0--响，1--不响

reg[5:0] cnt;

always @(posedge clk or negedge rst_m)
if(rst_m) cnt <=6'd0;
else if(cnt<49) cnt=cnt+1'b1;
else cnt=6'd0;

assign  fm=(cnt <= 6'd24)?1'b0:1'b1;

endmodule

[jiayou0909]

module ls1(clk,rst_m,fm); input clk;//时钟信号50MHZ input rst_m;//复位，低电平有效 output fm;//蜂鸣器 0--响，1--不响 reg [5:0]cnt; always @(posedge clk or negedge rst_m) if(!rst_m) cnt <= 6'd0; else if(cnt<49) cnt<=cnt+1'b1; else cnt<=6'd0; assign fm=(cnt <= 6'd24)?1'b0:1'b1; endmodule

[jiayou0909]

1. “reg(5:0) cnt;”中的()错了，应该为[]。 2. “cat”是笔误，应为cnt。 以上两个错误Quartus会报错，另外还要注意两点： 1. if(rst_m) 没有与敏感信号中的negedge rst_m对应，应该写成if(！rst_m) 或if(rst_m==1'b0). 2. always中的“=”最好改为“<=”。