数字电路八路抢答器清零问题

[kaitankedemao]

//clk:50MHZ的信号
//stu:8名抢答选手
//light:8名选手前的灯
//buzzer:蜂鸣器
//seg:七段显示译码器

//顶层模块
module qdq(clk,space,stu,light,buzzer,seg1,seg2,seg3,seg4);
input clk,space;
input[7:0] stu;
output[7:0] light;
output buzzer;
output[7:0] seg1;
output[7:0] seg2;
output[7:0] seg3;
output[7:0] seg4;

//分频
fenpin FA0(clk,~space,cp);
//计时
jishi FA1(cp,stu,space,en,buzzer,seg1,seg3,seg4,flag);
//抢答
qiangda FA2(stu,space,flag,light,seg2,en);
endmodule

//子模块
//因为试验箱上的时钟是50Mhz的，而倒计时模块中用到的是1hz和1khz的时钟，所以要分频
module fenpin(CLK, RST, clk_1Hz);
input CLK, RST;
output clk_1Hz;

wire clk_1MHz, clk_100KHz, clk_10KHz, clk_1KHz, clk_100Hz, clk_10Hz;

//assign clock = {clk_1MHz, clk_100KHz, clk_10KHz, clk_1KHz, clk_100Hz, clk_10Hz, clk_1Hz};

divide_by_50 d6 (clk_1MHz, CLK, RST);
divide_by_10 d5 (clk_100KHz, clk_1MHz, RST);
divide_by_10 d4 (clk_10KHz, clk_100KHz, RST);
divide_by_10 d3 (clk_1KHz, clk_10KHz, RST);
divide_by_10 d2 (clk_100Hz, clk_1KHz, RST);
divide_by_10 d1 (clk_10Hz, clk_100Hz, RST);
divide_by_10 d0 (clk_1Hz, clk_10Hz, RST);

endmodule



module divide_by_10 (Q, CLK, RST,);
input CLK, RST;
output Q;
reg Q;
reg [2:0] count;

always @(posedge CLK or negedge RST)
begin
if (~RST)
begin
Q <= 1'b0;
count <= 3'b000;
end
else if (count < 4)
begin
count <= count + 1'b1;
end
elsex
begin
count <= 3'b000;
Q <= ~Q;
end
end

endmodule


module divide_by_50 (Q, CLK, RST);
input CLK, RST;
output Q;
reg Q;
reg [4:0] count;

always @(posedge CLK or negedge RST)
begin
if (~RST)
begin
Q <= 1'b0;
count <= 5'b00000;
end
else if (count < 24)
begin
count <= count + 1'b1;
end
else
begin
count <= 5'b00000;
Q <= ~Q;
end
end

endmodule

//计时
//cp是1hz的信号
module jishi(cp,stu,space,en,buzzer,seg1,seg3,seg4,flag);
input cp,space,en;
input[7:0] stu;
output buzzer;
output[7:0] seg1;
output[7:0] seg3;
output[7:0] seg4;
output flag;
reg buzzer;
reg flag;
reg[4:0] count;
seg_7 FB1(tim,seg1);
seg_7 FB3(4'hf,seg3);
seg_7 FB4(4'hf,seg4);
always@(posedge cp or posedge space)
if(space)
begin
count=0;
buzzer=0;
flag=0;
if(stu[0]||stu[1]||stu[2]||stu[3]||stu[4]||stu[5]||stu[6]||stu[7])
buzzer=1;
end
else if(~space && en)
begin
if(count==9)
begin
buzzer=1;
flag=1;
end
else
count=count+1;
end
endmodule

//抢答
module qiangda(stu,space,flag,light,seg2,en);
input space,flag;
input[7:0] stu;
output[7:0] light;
output[7:0] seg2;
output en;
reg[7:0] light;
reg en;
wire[3:0] binary;
assign binary=light[0]+2*light[1]+3*light[2]+4*light[3]+5*light[4]+6*light[5]+7*light[6]+8*light[7];
seg_7 FB2(binary,seg2);
always@(stu or space)
if(space)
begin
en=1;
light=0;
end
else if(~space && en && ~flag)
begin
case(stu)
8'b00000001:begin light[0]=1;en=0;end
8'b00000010:begin light[1]=1;en=0;end
8'b00000100:begin light[2]=1;en=0;end
8'b00001000:begin light[3]=1;en=0;end
8'b00010000:begin light[4]=1;en=0;end
8'b00100000:begin light[5]=1;en=0;end
8'b01000000:begin light[6]=1;en=0;end
8'b10000000:begin light[7]=1;en=0;end
endcase
end
endmodule


//七段显示器
module seg_7(data,hex);
input[3:0] data;
output[7:0] hex;
reg[7:0] hex;
always@(data)
begin
case(data)
4'h0:hex=~8'h3F;
4'h1:hex=~8'h06;
4'h2:hex=~8'h5B;
4'h3:hex=~8'h4F;
4'h4:hex=~8'h66;
4'h5:hex=~8'h6D;
4'h6:hex=~8'h7D;
4'h7:hex=~8'h07;
4'h8:hex=~8'h7F;
4'h9:hex=~8'h67;
4'hf:hex=8'hFF;
endcase
end
endmodule


问题：
当选手抢答成功后，主持人将space置1可以将倒计时显示和选手组别显示的七段显示器清零，然后再将space置0开始新一轮的抢答。但是，现在的问题是，如果在主持人将space置0前刚刚抢答的选手未将抢答的开关关掉，新一轮的抢答不能开始这是正确的，但是倒计时的显示清零了而组别显示没有清零，我想让组别的也清零，这该怎么改？？？


求大神帮助指导啊！！课设截止时间快到了QAQ

[a834091709]

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