VHDL语言程序报错，求大神指点

cwhe_10 2014-05-14 01:11:54

library ieee;
use ieee.std_logic.all;
use ieee.std_logic_unsigned.all;

entity bisou is
port(a:in std_logic;
reset:in std_logic;
h1:out std_logic);
end bisou;
architecture bisou1 of bisou is
begin
u1:process(a)
begin
if(a'event and a='1') then
h1<='1';
end if;
end process u1;
u2:process(reset)
begin
if(reset='1') then
h1<='0';
end if;
end process u2;
end bisou1; --u1 end

library ieee; --u2 start
use ieee.std_logic.all;
use ieee.std_logic_unsigned.all;

entity bisou2 is
port(clk:in std_logic;
h2:in std_logic;
fre:out std_logic;
reset2:buffer std_logic);
end bisou2;
architecture bisou2 of bisou2 is
SIGNAL cnt1 : std_logic_vector(10 DOWNTO 0); --shu chu gei bell
SIGNAL cnt2 : std_logic_vector(21 DOWNTO 0); --yan shi 2s hou reset=0
signal fr_low: std_logic;
signal fr_high: std_logic;
begin
fre<=fr_low;
reset2<=fr_high;
u2:process(h2,clk)
begin
if h2='0' then cnt1<="00000000000";
elsif (clk'event and clk=1) then
if cnt1="11111111111" then cnt1<="00000000000";
else cnt1=cnt1+'1';
end if;
end if;
end process u2;

u3:process(h2,clk)
begin
if h2='0' then cnt2<="0000000000000000000000";
elsif (clk'event and clk='1') then
if cnt2="1111111111111111111111" then cnt2<="0000000000000000000000";
else cnt2=cnt2+'1';
end if;
end if;
end process u3;

u4:process(cnt1)
begin
if cnt1="11111111111" then fr_low<=not fr_low;
end if;
end process u4;

u5:process(cnt2,cnt1)
begin
if cnt2="1111111111111111111111" then
fre_high<='1';
cnt2<="0000000000000000000000";
cnt1<="00000000000";
else fre_high<='0';
end if;
end process u5;
end bisou2; --u2 end

library ieee; --u2+u1 start
use ieee.std_logic.all;
use ieee.std_logic_unsigned.all;

entity bisou3 is
port(a:in std_logic;
b:in std_logic;
clk:in std_logic;
fre_low:out std_logic;
buff:buffer std_logic);
end bisou3;
architecture bisou3 of bisou3 is
signal tem1,temp2:std_logic;
component bisou
port(a1:in std_logic;
reset:in std_logic;
h1:out std_logic);
end component;

component bisou2
port(clk:in std_logic;
h2:in std_logic;
fre:out std_logic
reset2:buffer std_logic);
end component;
begin
u0:bisou port map(a1,temp2,temp1);
u1:bisou2 port map(clk,temp1,fre_low,temp2);
end bisou3;

管脚说明：系统功能为检测第一个实体bisou的输入管教a，a一旦有上升沿，就使输出h1为高电平，其中第一实体bisou的reset为复位管脚，reset为1时，会使h1为低电平。。。。第二个实体bisou2有一个时钟输入管脚clk，另一个h2（其实在第三个实体里，实现h1和h2连接），当h2为高电平时，开始计数，输出fre管脚是一定频率的，另一个输出reset2为高频率计数，当达到最高计数时，其为1，因为实现reset2与第一个实体的复位信号reset连接，而使得其可以反馈控制h1.。。。

程序报错4个地方，求大神指点？

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