use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bisou is
port(a:in std_logic;
b:in std_logic;
y1:out std_logic);
end bisou;
architecture bisou of bisou is
signal u:std_logic_vector(1 downto 0);
begin
u(0)<=a;
u(1)<=b;
y1<='1' when u="10" else
'0' when u="01" else
'Z';
end bisou;
library ieee; --u2 start
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bisou2 is
port(clk:in std_logic;
b:in std_logic;
y1:out std_logic;
y2:buffer std_logic);
end bisou2;
architecture bisou2 of bisou2 is
SIGNAL cnt1 : std_logic_vector(10 DOWNTO 0); --shu chu gei bell
SIGNAL cnt2 : std_logic_vector(14 DOWNTO 0); --yan shi 2s hou reset=0
signal fr_low: std_logic;
signal fr_high: std_logic;
begin
y1<=fr_low;
y2<=fr_high;
u2:process(b,clk)
begin
if b='0' then cnt1<="00000000000";
elsif (clk'event and clk='1') then
if cnt1="11111111111" then cnt1<="00000000000";
else cnt1<=cnt1+'1';
end if;
end if;
end process u2;
u3:process(b,clk)
begin
if b='0' then cnt2<="000000000000000";
elsif (clk'event and clk='1') then
if cnt2="111111111111111" then cnt2<="000000000000000";
else cnt2<=cnt2+'1';
end if;
end if;
end process u3;
u4:process(cnt1)
begin
if cnt1="11111111111" then fr_low<=not fr_low;
end if;
end process u4;
u5:process(cnt2,cnt1)
begin
if cnt2="111111111111111" then
y1<='1';
cnt2<="000000000000000";
cnt1<="00000000000";
else y2<='0';
end if;
end process u5;
end bisou2; --u2 end
library ieee; --u2+u1 start
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bisou3 is
port(clk:in std_logic;
a:in std_logic;
y1:out std_logic);
end bisou3;
architecture bisou3 of bisou3 is
signal temp1,temp2:std_logic;
component bisou
port(a:in std_logic;
b:in std_logic;
y:out std_logic);
end component;
component bisou2
port(clk:in std_logic;
b:in std_logic;
y1:out std_logic;
y2:buffer std_logic);
end component;
begin
u0:bisou port map(a,temp2,temp1);
u1:bisou2 port map(clk,temp1,y1,temp2);
end bisou3;
进行仿真时，仿真的管脚总是第一个实体的管脚（a，b，y），而不是我要的第三个实体的管脚号（clk,a,y1),这是为什么呢？
