basys2 数码管动态显示 verilog

ryan153770 2014-10-26 11:08:02

为什么数码管动态显示定义的管脚顺序和我设计的是反的~~求助啊在线等！！！！！
输入x[3:0]显示的是最左边的管子
basys2板子~~~~
约束文件
NET "clk" LOC=B8;
NET "x[0]" LOC=P11; 开关最右边
NET "x[1]" LOC=L3;
NET "x[2]" LOC=K3;
NET "x[3]" LOC=B4;
NET "x[4]" LOC=G3;
NET "x[5]" LOC=F3;
NET "x[6]" LOC=E2;
NET "x[7]" LOC=N3; 开关最左边
NET "a_to_g[0]" LOC=M12;
NET "a_to_g[1]" LOC=L13;
NET "a_to_g[2]" LOC=P12;
NET "a_to_g[3]" LOC=N11;
NET "a_to_g[4]" LOC=N14;
NET "a_to_g[5]" LOC=H12;
NET "a_to_g[6]" LOC=L14;
NET "an[0]" LOC=K14; 数码管最右边的管子
NET "an[1]" LOC=M13;
NET "an[2]" LOC=J12;
NET "an[3]" LOC=F12; 数码管最左边的管子

顶层模块
module top(
input clk,
input[7:0]x,
output[3:0]an,
output reg[6:0]a_to_g
);
wire clk_div;
wire[1:0]s; //此时哪个数码管亮灯
reg[3:0] digit;
reg[4:0]temp;
clkdiv u0(.clk(clk),.div(clk_div));
enabled u1(.clkdiv(clk_div),.an(an),.n(s));
always@(*)
begin
case(s)
0: digit=x[3:0];
1: digit=x[3:0];
2: digit=x[7:4];
3: digit=x[7:4];
endcase
end
always@(*)
begin
temp=to8421(digit);
if(temp[4]==0)
begin
case(s)
0:a_to_g=display(temp[3:0]);
1:a_to_g=7*b0000001;
2:a_to_g=display(temp[3:0]);
3:a_to_g=7*b0000001;
endcase
end
else if(temp[4]==1)
begin
case(s)
0:a_to_g=display(temp[3:0]);
1:a_to_g=7*b1001111;
2:a_to_g=display(temp[3:0]);
3:a_to_g=7*b1001111;
endcase
end
end

function [6:0]display;
input[3:0]x;
begin
case(x)
0:display=7*b0000001;
1:display=7*b1001111;
2:display=7*b0010010;
3:display=7*b0000110;
4:display=7*b1001100;
5:display=7*b0100100;
6:display=7*b0100000;
7:display=7*b0001111;
8:display=7*b0000000;
9:display=7*b0000100;
*hA:display=7*b0001000;
*hB:display=7*b1100000;
*hC:display=7*b0110001;
*hD:display=7*b1000010;
*hE:display=7*b0110000;
*hF:display=7*b0111000;
default:display=7*b0000001; //0
endcase
end
endfunction
function [4:0]to8421;
input[3:0]x;
begin
case(x)
0:to8421=5*b00000;
1:to8421=5*b00001;
2:to8421=5*b00010;
3:to8421=5*b00011;
4:to8421=5*b00100;
5:to8421=5*b00101;
6:to8421=5*b00110;
7:to8421=5*b00111;
8:to8421=5*b01000;
9:to8421=5*b01001;
*hA:to8421=5*b10000;
*hB:to8421=5*b10001;
*hC:to8421=5*b10010;
*hD:to8421=5*b10011;
*hE:to8421=5*b10100;
*hF:to8421=5*b10101;
endcase
end
endfunction
endmodule

时钟模块
//生成周期为5.2ms的时钟
module clkdiv(
input clk,
output reg div
);
reg[16:0]s;
always@(posedge clk)
begin
if (s==130000)
begin s<=0; div=~div; end
else
s<=s+1;
end
endmodule

使能模块
//使四个数码管依次连续使能
module enabled(
input clkdiv,
output reg[3:0]an,
output reg[1:0]n
);
reg[1:0]q;
always@(posedge clkdiv)
begin
if(q==3) q<=0;
else q<=q+1;
end
always@(*)
begin
an=4*b1111;
case(q)
0:begin an=4*b1110; n=0; end
1:begin an=4*b1101; n=1; end
2:begin an=4*b1011; n=2; end
3:begin an=4*b0111; n=3; end
default:an=4*b1111; //禁止数码管显示
endcase
end
endmodule

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