OpenGL 4 Shader Subroutines - NVIDIA/OSX bug?

妈妈说女孩子要自立自强 2014-11-23 11:28:32

今天在做opengl中的阴影的时候，感觉貌似发现了OSX+NVIDIA上的opengl的一个bug。。。

事情是这样的，由于阴影需要两个pass渲染，因此想在shader中使用subroutine，但奇怪的是在C++代码里用glUniformSubroutinesuiv没有用。怀疑了很久是自己的问题，但跟红宝书对了很多遍代码，还是发现不了问题，于是偶然发现了这个帖子：
http://www.geeks3d.com/forums/index.php?topic=3730.0

这位老兄遇到了跟我类似的问题，简单来说就是在其他电脑上都能跑对的程序，在NVIDIA GeForce GT 650M OS X 10.9就是没法设置subroutine。

这就意味着，这是个硬件错误。但硬件错误是非常严重的吧，怎么会到现在都没有修复呢？有其他人遇到同样的情况吗？

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彩阳 2015-01-22

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听说GTX6XX系列并不好。换GT7XX系列吧。

kagada 2015-01-15

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你是苹果电脑啊，那我不知道行不行，我在windows下用Aida64看我的显卡对opengl的支持，opengl4.0是100%，opengl4.1是85%，我的显卡是gtx660m，比你这个要好一点，你这个打印出来的信息是不是不完整或者有误啊。

妈妈说女孩子要自立自强 2014-12-31

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引用 1 楼 I_believe328 的回复:

glUniformSubroutinesuiv 需要Opengl版本最低4.0，可能是N650M显卡驱动支持的版本<4.0

额，竟然有人回复了，好感动~不过应该不是版本的问题，我输出了显卡和GL的相关信息： GL Vendor : NVIDIA Corporation GL Renderer : NVIDIA GeForce GT 650M OpenGL Engine GL Version : 4.1 NVIDIA-8.26.28 310.40.55b01 GL Version : 4.1 GLSL Version : 4.10 应该是支持的

I_believe328 2014-12-31

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glUniformSubroutinesuiv 需要Opengl版本最低4.0，可能是N650M显卡驱动支持的版本<4.0

本文讲述如何在MDK（keil）中将1个子程序段定位在1个固定的地址位置。

Abaqus 用户单元子程序UEL Fortran程序开发

S7300 SUBROUTINES(INCLUDE PID/GD COMM/CP340 COMMrar,S7300 SUBROUTINES(INCLUDE PID/GD COMM/CP340 COMM

writing subroutine with abaqus

Complete Digital Design - A Comprehensive Guide to Digital Electronics and Computer System Architecture PART 1 Digital Fundamentals Chapter 1 Digital Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Boolean Logic / 3 1.2 Boolean Manipulation / 7 1.3 The Karnaugh map / 8 1.4 Binary and Hexadecimal Numbering / 10 1.5 Binary Addition / 14 1.6 Subtraction and Negative Numbers / 15 1.7 Multiplication and Division / 17 1.8 Flip-Flops and Latches / 18 1.9 Synchronous Logic / 21 1.10 Synchronous Timing Analysis / 23 1.11 Clock Skew / 25 1.12 Clock Jitter / 27 1.13 Derived Logical Building Blocks / 28 Chapter 2 Integrated Circuits and the 7400 Logic Families. . . . . . . . . . . . . . . . . . . . .33 2.1 The Integrated Circuit / 33 2.2 IC Packaging / 38 2.3 The 7400-Series Discrete Logic Family / 41 2.4 Applying the 7400 Family to Logic Design / 43 2.5 Synchronous Logic Design with the 7400 Family / 45 2.6 Common Variants of the 7400 Family / 50 2.7 Interpreting a Digital IC Data Sheet / 51 Chapter 3 Basic Computer Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.1 The Digital Computer / 56 3.2 Microprocessor Internals / 58 3.3 Subroutines and the Stack / 60 3.4 Reset and Interrupts / 62 3.5 Implementation of an Eight-Bit Computer / 63 3.6 Address Banking / 67 3.7 Direct Memory Access / 68 3.8 Extending the Microprocessor Bus / 70 3.9 Assembly Language and Addressing Modes / 72 Chapter 4 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 4.1 Memory Classifications / 77 4.2 EPROM / 79 4.3 Flash Memory / 81 4.4 EEPROM / 85 4.5 Asynchronous SRAM / 86 4.6 Asynchronous DRAM / 88 4.7 Multiport Memory / 92 4.8 The FIFO / 94 Chapter 5 Serial Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 5.1 Serial vs. Parallel Communication / 98 5.2 The UART / 99 5.3 ASCII Data Representation / 102 5.4 RS-232 / 102 5.5 RS-422 / 107 5.6 Modems and Baud Rate / 108 5.7 Network Topologies / 109 5.8 Network Data Formats / 110 5.9 RS-485 / 112 5.10 A Simple RS-485 Network / 114 5.11 Interchip Serial Communications / 117 Chapter 6 Instructive Microprocessors and Microcomputer Elements . . . . . . . . . .121 6.1 Evolution / 121 6.2 Motorola 6800 Eight-bit Microprocessor Family / 122 6.3 Intel 8051 Microcontroller Family / 125 6.4 Microchip PIC® Microcontroller Family / 131 6.5 Intel 8086 16-Bit Microprocessor Family / 134 6.6 Motorola 68000 16/32-Bit Microprocessor Family / 139 PART 2 Advanced Digital Systems Chapter 7 Advanced Microprocessor Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 7.1 RISC and CISC / 145 7.2 Cache Structures / 149 7.3 Caches in Practice / 154 7.4 Virtual Memory and the MMU / 158 7.5 Superpipelined and Superscalar Architectures / 161 7.6 Floating-Point Arithmetic / 165 7.7 Digital Signal Processors / 167 7.8 Performance Metrics / 169 Chapter 8 High-Performance Memory Technologies. . . . . . . . . . . . . . . . . . . . . . . . .173 8.1 Synchronous DRAM / 173 8.2 Double Data Rate SDRAM / 179 8.3 Synchronous SRAM / 182 8.4 DDR and QDR SRAM / 185 8.5 Content Addressable Memory / 188 Chapter 9 Networking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 9.1 Protocol Layers One and Two / 193 9.2 Protocol Layers Three and Four / 194 9.3 Physical Media / 197 9.4 Channel Coding / 198 9.5 8B10B Coding / 203 9.6 Error Detection / 207 9.7 Checksum / 208 9.8 Cyclic Redundancy Check / 209 9.9 Ethernet / 215 Chapter 10 Logic Design and Finite State Machines . . . . . . . . . . . . . . . . . . . . . . . . .221 10.1 Hardware Description Languages / 221 10.2 CPU Support Logic / 227 10.3 Clock Domain Crossing / 233 10.4 Finite State Machines / 237 10.5 FSM Bus Control / 239 10.6 FSM Optimization / 243 10.7 Pipelining / 245 Chapter 11 Programmable Logic Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 11.1 Custom and Programmable Logic / 249 11.2 GALs and PALs / 252 11.3 CPLDs / 255 11.4 FPGAs / 257 PART 3 Analog Basics for Digital Systems Chapter 12 Electrical Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 12.1 Basic Circuits / 267 12.2 Loop and Node Analysis / 268 12.3 Resistance Combination / 271 12.4 Capacitors / 272 12.5 Capacitors as AC Elements / 274 12.6 Inductors / 276 12.7 Nonideal RLC Models / 276 12.8 Frequency Domain Analysis / 279 12.9 Lowpass and Highpass Filters / 283 12.10 Transformers / 288 Chapter 13 Diodes and Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 13.1 Diodes / 293 13.2 Power Circuits with Diodes / 296 13.3 Diodes in Digital Applications / 298 13.4 Bipolar Junction Transistors / 300 13.5 Digital Amplification with the BJT / 301 13.6 Logic Functions with the BJT / 304 13.7 Field-Effect Transistors / 306 13.8 Power FETs and JFETs / 309 Chapter 14 Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311 14.1 The Ideal Op-amp / 311 14.2 Characteristics of Real Op-amps / 316 14.3 Bandwidth Limitations / 324 14.4 Input Resistance / 325 14.5 Summation Amplifier Circuits / 328 14.6 Active Filters / 331 14.7 Comparators and Hysteresis / 333 Chapter 15 Analog Interfaces for Digital Systems . . . . . . . . . . . . . . . . . . . . . . . . . . .339 15.1 Conversion between Analog and Digital Domains / 339 15.2 Sampling Rate and Aliasing / 341 15.3 ADC Circuits / 345 15.4 DAC Circuits / 348 15.5 Filters in Data Conversion Systems / 350 PART 4 Digital System Design in Practice Chapter 16 Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355 16.1 Crystal Oscillators and Ceramic Resonators / 355 16.2 Low-Skew Clock Buffers / 357 16.3 Zero-Delay Buffers: The PLL / 360 16.4 Frequency Synthesis / 364 16.5 Delay-Locked Loops / 366 16.6 Source-Synchronous Clocking / 367 Chapter 17 Voltage Regulation and Power Distribution . . . . . . . . . . . . . . . . . . . . . .371 17.1 Voltage Regulation Basics / 372 17.2 Thermal Analysis / 374 17.3 Zener Diodes and Shunt Regulators / 376 17.4 Transistors and Discrete Series Regulators / 379 17.5 Linear Regulators / 382 17.6 Switching Regulators / 386 17.7 Power Distribution / 389 17.8 Electrical Integrity / 392 Chapter 18 Signal Integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397 18.1 Transmission Lines / 398 18.2 Termination / 403 18.3 Crosstalk / 408 18.4 Electromagnetic Interference / 410 18.5 Grounding and Electromagnetic Compatibility / 413 18.6 Electrostatic Discharge / 415 Chapter 19 Designing for Success . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419 19.1 Practical Technologies / 420 19.2 Printed Circuit Boards / 422 19.3 Manually Wired Circuits / 425 19.4 Microprocessor Reset / 428 19.5 Design for Debug / 429 19.6 Boundary Scan / 431 19.7 Diagnostic Software / 433 19.8 Schematic Capture and Spice / 436 19.9 Test Equipment / 440 Appendix A Further Education. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .443 Index 445

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