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分享求verilog设计的四位十进制数加减乘除计算器源代码和实验报告，请发到zjuwh@sina.cn，谢谢。
求verilog设计的四位十进制数加减乘除计算器源代码和实验报告，请发到zjuwh@sina.cn，要求如下：
Implement a decimal calculator,operate addition, subtraction, multiplication and division for two 16 bits numbers and display the results in 7-segment LED display.Using decimal numbers as the inputs/outputs. Each input is 4 decimals (16 bits).Display an error message (ERR)when the divisor is 0.Please make your own user interact design to control the calculation operation, to display the operation results,and provide the clear user manual. Build Behavioral Simulation and submit the simulation results.
Implement a decimal calculator,operate addition, subtraction, multiplication and division for two 16 bits numbers and display the results in 7-segment LED display.Using decimal numbers as the inputs/outputs. Each input is 4 decimals (16 bits).Display an error message (ERR)when the divisor is 0.Please make your own user interact design to control the calculation operation, to display the operation results,and provide the clear user manual. Build Behavioral Simulation and submit the simulation results.
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bingzhongxing 2017-03-21
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您好 请问一下你的代码还在吗 Verilog 计算器 可否发给我一下 642034905@qq.com
zjuujz 2015-06-01
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已发代码，请验收。
zjuujz2 2015-05-31
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改为：
module caculator(clk, btn_in,sw, led,digit_anode, segment);
input clk;
input [2:0] sw;
input [3:0] btn_in;
output [3:0] digit_anode;
output [ 7:0] segment;
wire clk_1ms;
wire [3:0] btn_in;
wire [3:0] digit_anode;
wire [7:0] segment;
reg [15:0] disp_num;
wire [3:0] btn_out;
reg [8:1] A,B;
initial begin
A<=8'b0000_0000;
B<=8'b0000_0000;
end
anti_jitter I1 (clk,clk_1ms,btn_in,btn_out);
Timer_1ms I2 (clk,clk_1ms);
always@(posedge btn_out[0]) B[ 4: 1]<=B[ 4: 1] + 4'd1;
always@(posedge btn_out[1]) B[ 8: 5]<=B[ 8: 5] + 4'd1;
always@(posedge btn_out[2]) A[ 4: 1]<=A[ 4: 1] + 4'd1;
always@(posedge btn_out[3]) A[ 8: 5]<=A[ 8: 5] + 4'd1;
cal ca(A,B,sw,disp_num);
display DISPLAY_0(clk, disp_num,digit_anode, segment);
endmodule
module cal (a,b,sw,result);
input [8:1] a;
input [8:1] b;
input [2:0] sw;
output [15:0] result;
reg [15:0] result;
always@(sw or a or b)begin
case(sw)
000:begin result={a[8:1], b[8:1]};end
001:begin result=a+b;end
010:begin if(a<b) result={4’b1010,b-a}; else result=a-b;end
011:begin result=a*b;end
100:begin if(b!=0)result=a/b;else begin result=12’b101111001100;end
default: result=0;
endcase
end
endmodule
module display(clk,digit,node,segment);
input wire clk;
input wire [15:0] digit;
output reg [ 3:0] node;
output reg [ 7:0] segment;
reg [3:0] code = 4'b0;
reg [15:0] count = 15'b0;
always @(posedge clk)begin
case (count[15:14])
2'b00 : begin
node <= 4'b1110;
code <= digit[3:0];
end
2'b01 : begin
node <= 4'b1101;
code <= digit[7:4];
end
2'b10 : begin
node <= 4'b1011;
code <= digit[11:8];
end
2'b11 : begin
node <= 4'b0111;
code <= digit[15:12];
end
endcase
case (code)
4'b0000: segment <= 8'b11000000;
4'b0001: segment <= 8'b11111001;
4'b0010: segment <= 8'b10100100;
4'b0011: segment <= 8'b10110000;
4'b0100: segment <= 8'b10011001;
4'b0101: segment <= 8'b10010010;
4'b0110: segment <= 8'b10000010;
4'b0111: segment <= 8'b11111000;
4'b1000: segment <= 8'b10000000;
4'b1001: segment <= 8'b10010000;
4’b1010: segment <= 8’b10111111;
4’b1011: segment <= 8’b10000110;
4’b1100: segment <= 8’b10001000;
default: segment <= 8'b11111111;
endcase
count <= count + 1;
end
endmodule
module anti_jitter(clk, clk_1ms, btn, btn_out);
input clk;
input clk_1ms;
input [3:0] btn;
output [3:0] btn_out;
wire clk, clk_1ms;
wire [3:0] btn;
reg [3:0] btn_out;
reg [3:0] cnt_aj;
reg [3:0] btn_old;
initial begin
cnt_aj <= 0;
btn_out <= 4'b0000;
btn_old <= 4'b0000;
end
always @(posedge clk) begin
if (btn != btn_old) begin
cnt_aj <= 4'b0000;
btn_old <= btn;
end
else begin
if (clk_1ms) begin
if (cnt_aj == 4'b1111) begin
cnt_aj <= 4'b0000;
btn_out <= btn;
end
cnt_aj <= cnt_aj + 1;
end
end
end
endmodule
module Timer_1ms(clk, clk_1ms); //1ms timer
input clk;
output clk_1ms;
wire clk;
reg clk_1ms;
reg [15:0] cnt;
initial begin
cnt [15:0] <= 0;
end
always @(posedge clk) begin
if (cnt >= 49999) begin
cnt <= 0;
clk_1ms <= 1;
end
else begin
cnt <= cnt + 1;
clk_1ms <= 0;
end
end
endmodule
UCF:
Net "clk" loc = "T9";
net "segment[0]" loc = "E14";
net "segment[1]" loc = "G13";
net "segment[2]" loc = "N15";
net "segment[3]" loc = "P15";
net "segment[4]" loc = "R16";
net "segment[5]" loc = "F13";
net "segment[6]" loc = "N16";
net "segment[7]" loc = "P16";
net "digit_anode[0]" loc = "D14";
net "digit_anode[1]" loc = "G14";
net "digit_anode[2]" loc = "F14";
net "digit_anode[3]" loc = "E13";
net "btn_in[0]" loc = "L14";
net "btn_in[1]" loc = "L13";
net "btn_in[2]" loc = "M14";
net "btn_in[3]" loc = "M13";
net "sw[0]" loc = "F12";
net "sw[1]" loc = "G12";
net "sw[2]" loc = "H14";
zjuujz2 2015-05-30
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自己写了一个，求指教。
module caculator(clk, btn_in,sw, led,digit_anode, segment);
input clk;
input [2:0] sw;
input [3:0] btn_in;
output [3:0] digit_anode;
output [ 7:0] segment;
wire clk_1ms;
wire [3:0] btn_in;
wire [3:0] digit_anode;
wire [7:0] segment;
reg [15:0] disp_num;
wire [3:0] btn_out;
reg [8:1] A,B;
reg signal,err;
initial begin
A<=8'b0000_0000;
B<=8'b0000_0000;
end
anti_jitter I1 (clk,clk_1ms,btn_in,btn_out);
Timer_1ms I2 (clk,clk_1ms);
always@(posedge btn_out[0]) B[ 4: 1]<=B[ 4: 1] + 4'd1;
always@(posedge btn_out[1]) B[ 8: 5]<=B[ 8: 5] + 4'd1;
always@(posedge btn_out[2]) A[ 4: 1]<=A[ 4: 1] + 4'd1;
always@(posedge btn_out[3]) A[ 8: 5]<=A[ 8: 5] + 4'd1;
cal ca(A,B,sw,signal,err,disp_num);
display DISPLAY_0(clk, disp_num,signal,err,digit_anode, segment);
endmodule
module cal (a,b,sw,signal,err,result);
input [8:1] a;
input [8:1] b;
input [2:0] sw;
output [15:0] result;
output signal,err;
reg [15:0] result;
reg signal,err;
initial begin
signal<=0;
err<=0;
end
always@(sw or a or b)begin
case(sw)
000:begin result={a[8:1], b[8:1]};end
001:begin result=a+b;end
010:begin if(a<b)begin result=b-a;signal=1;end else result=a-b; 011:begin result=a*b;end
100:begin if(b!=0)result=a/b;else begin result=0;err=1;end
default: result=0;
endcase
end
endmodule
module display(clk,digit,signal,err,node,segment);
input wire clk;
input wire [15:0] digit;
input signal,err;
output reg [ 3:0] node;
output reg [ 7:0] segment;
reg [3:0] code = 4'b0;
reg [15:0] count = 15'b0;
always @(posedge clk)begin
if(err)begin node<=4’b1110;segment<=8’b10001000;node<=4’b1101;segment<=8’b10001000;node<=4’b1011;segment<=8’b10000110;end else begin
case (count[15:14])
2'b00 : begin
node <= 4'b1110;
code <= digit%4’d10;
end
2'b01 : begin
node <= 4'b1101;
code <= digit/4’d10%4’d10;
end
2'b10 : begin
node <= 4'b1011;
code <= digit/4’d100%4’d10;
end
2'b11 : begin
node <= 4'b0111;
code <= digit/4’d1000%4’d10;
end
endcase
if(signal) begin node<=4’b0111;segment<=8’b10111111;end else
case (code)
4'b0000: segment <= 8'b11000000;
4'b0001: segment <= 8'b11111001;
4'b0010: segment <= 8'b10100100;
4'b0011: segment <= 8'b10110000;
4'b0100: segment <= 8'b10011001;
4'b0101: segment <= 8'b10010010;
4'b0110: segment <= 8'b10000010;
4'b0111: segment <= 8'b11111000;
4'b1000: segment <= 8'b10000000;
4'b1001: segment <= 8'b10010000;
default: segment <= 8'b00000000;
endcase
end
count <= count + 1;
end
endmodule
module anti_jitter(clk, clk_1ms, btn, btn_out);
input clk;
input clk_1ms;
input [3:0] btn;
output [3:0] btn_out;
wire clk, clk_1ms;
wire [3:0] btn;
reg [3:0] btn_out;
reg [3:0] cnt_aj;
reg [3:0] btn_old;
initial begin
cnt_aj <= 0;
btn_out <= 4'b0000;
btn_old <= 4'b0000;
end
always @(posedge clk) begin
if (btn != btn_old) begin
cnt_aj <= 4'b0000;
btn_old <= btn;
end
else begin
if (clk_1ms) begin
if (cnt_aj == 4'b1111) begin
cnt_aj <= 4'b0000;
btn_out <= btn;
end
cnt_aj <= cnt_aj + 1;
end
end
end
endmodule
module Timer_1ms(clk, clk_1ms); //1ms timer
input clk;
output clk_1ms;
wire clk;
reg clk_1ms;
reg [15:0] cnt;
initial begin
cnt [15:0] <= 0;
end
always @(posedge clk) begin
if (cnt >= 49999) begin
cnt <= 0;
clk_1ms <= 1;
end
else begin
cnt <= cnt + 1;
clk_1ms <= 0;
end
end
endmodule
UCF:
Net "clk" loc = "T9";
net "segment[0]" loc = "E14";
net "segment[1]" loc = "G13";
net "segment[2]" loc = "N15";
net "segment[3]" loc = "P15";
net "segment[4]" loc = "R16";
net "segment[5]" loc = "F13";
net "segment[6]" loc = "N16";
net "segment[7]" loc = "P16";
net "digit_anode[0]" loc = "D14";
net "digit_anode[1]" loc = "G14";
net "digit_anode[2]" loc = "F14";
net "digit_anode[3]" loc = "E13";
net "btn_in[0]" loc = "L14";
net "btn_in[1]" loc = "L13";
net "btn_in[2]" loc = "M14";
net "btn_in[3]" loc = "M13";
net "sw[0]" loc = "F12";
net "sw[1]" loc = "G12";
net "sw[2]" loc = "H14";
zjuujz2 2015-05-22
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平台要求是XilinxSpartan的，求VerilogHDL代码和ucf文件。
falloutmx 2015-03-05
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给你几个链接去下载吧
http://www.pudn.com/downloads138/sourcecode/others/detail593688.html
http://www.cnblogs.com/woshitianma/archive/2012/12/10/2811800.html
http://download.csdn.net/detail/wbjdsj/3941958
用户 昵称 2015-03-05
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