quartus ii中的VHDL文件编译错误
VHDL程序为(上升沿D触发器):
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DFF1 IS
PORT(CLK:IN STD_LOGIC;
D:IN STD_LOGIC;
Q:OUT STD_LOGIC);
END;
ARCHITECTURE bhv OF DEF1 IS
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1'
THEN Q<=D;
END IF;
END PROCESS;
END bhv;
编译显示Error (10334): VHDL error at DEF.vhd(8): entity "DEF1" is used but not declared。。。怎么办