谁能给我解释一下这个电路图

[Hhy_Just_Code_It]

电路图的描述如下
Figure 1 illustrates a silicon PUF delay circuit based on
MUXes and an arbiter. The circuit has a multiple-bit input
X and computes a 1-bit output Y based on the relative delay
difference between two paths with the same layout length.
The input bits determine the delay paths by controlling the
MUXes. Here, a pair of MUXes controlled by the same input
bit X[i] work as a switching box (dotted boxes in the figure).
The MUXes pass through the two delay signals from the left
side if the input control bit X[i] is zero. Otherwise, the top
and bottom signals are switched. In this way, the circuit can
create a pair of delay paths for each input X.Toevaluate
the output for a particular input, a rising signal is given to
both paths at the same time, the signals race through the
two delay paths, and the arbiter (latch) at the end decides
which signal is faster. The output is one if the signal to the
latch data input (D) is faster, and zero otherwise.

大部分能理解，可是中间这个MUX如何工作的无法理解，MUX不是数据选择器吗，在这里如何使用啊。

[Hhy_Just_Code_It]

有人给回答一下吗

[fuchouzhe]

用于数字延时路径的举例而已

[Hhy_Just_Code_It]

楼上能具体说说吗？ 信号怎么通过MUX的，延时在哪里产生

[Hhy_Just_Code_It]

求助啊！！！！！！！！！！1

[fuchouzhe]

除非虚拟元件，否则都有延迟，这里利用切换器进行举例而已。