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always@(posedge clk)
begin
if(!rst)
begin
spi_cs_data_reg1<=0;
end
else
begin
spi_cs_data_reg1<=spi_cs_data;
end
end
always@(posedge clk)
begin
if(!rst)
begin
spi_cs_data_reg<=0;
end
else
begin
spi_cs_data_reg<=spi_cs_data_reg1;
end
end