vhdl的 couldn't implement registers for assignments on this clock edge问题

wingcmos 2016-08-24 12:48:23
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY hc_sr04 IS
PORT(
CLK :IN STD_LOGIC;
ECHO0 :IN STD_LOGIC;
ECHO1 :IN STD_LOGIC;
ECHO2 :IN STD_LOGIC;
ECHO3 :IN STD_LOGIC;
ECHO4 :IN STD_LOGIC;
ECHO5 :IN STD_LOGIC;
ECHO6 :IN STD_LOGIC;
ECHO7 :IN STD_LOGIC;
TRIG0 :OUT STD_LOGIC;
TRIG1 :OUT STD_LOGIC;
TRIG2 :OUT STD_LOGIC;
TRIG3 :OUT STD_LOGIC;
TRIG4 :OUT STD_LOGIC;
TRIG5 :OUT STD_LOGIC;
TRIG6 :OUT STD_LOGIC;
TRIG7 :OUT STD_LOGIC;
DIS0 :OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DIS1 :OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DIS2 :OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DIS3 :OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DIS4 :OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DIS5 :OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DIS6 :OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DIS7 :OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
END hc_sr04;

ARCHITECTURE behave OF hc_sr04 IS
TYPE state IS (s0,trig,wfor,echo,outdis);
SIGNAL cs :state :=s0;
SIGNAL S_TRIG :STD_LOGIC_VECTOR(7 DOWNTO 0) :="00000001";
SIGNAL cnt :INTEGER := 0;

BEGIN
COM1:PROCESS(cs,CLK)
VARIABLE cnt1,cnt2,cnt3 :INTEGER RANGE 0 TO 3 := 0;
BEGIN
CASE cs IS
WHEN s0 => IF cnt1 /= 3 THEN
IF CLK'EVENT AND CLK = '1' THEN
cnt1 := cnt1 + 1;
END IF;
ELSE
cnt1 := 0;
cs <= trig;
END IF;
WHEN trig => IF cnt2 /= 2 THEN
IF CLK'EVENT AND CLK = '1' THEN
cnt2 := cnt2 + 1;
END IF;
ELSE
cnt2 := 0;
cs <= wfor;
END IF;
WHEN wfor => IF ECHO0 = '1' OR ECHO1 = '1' OR ECHO2 = '1'
OR ECHO3 = '1' OR ECHO4 = '1' OR ECHO5 = '1'
OR ECHO6 = '1' OR ECHO7 = '1' THEN
cs <= echo;
END IF;
WHEN echo => IF ECHO0 = '0' AND ECHO1 = '0' AND ECHO2 = '0'
AND ECHO3 = '0' AND ECHO4 = '0' AND ECHO5 = '0'
AND ECHO6 = '0' AND ECHO7 = '0' THEN
cs <= outdis;
END IF;
WHEN outdis => IF cnt3 /= 3 THEN
IF CLK'EVENT AND CLK = '1' THEN
cnt3 := cnt3 + 1;
END IF;
ELSE
cnt3 := 0;
cs <= s0;
END IF;
WHEN others => NULL;
END CASE;
END PROCESS;
COM2:PROCESS(cs,CLK)
BEGIN
CASE cs IS
WHEN S0 =>
CASE S_TRIG IS
WHEN "00000001" => S_TRIG <= "00000010"; cnt <= 0;
WHEN "00000010" => S_TRIG <= "00000100"; cnt <= 0;
WHEN "00000100" => S_TRIG <= "00001000"; cnt <= 0;
WHEN "00001000" => S_TRIG <= "00010000"; cnt <= 0;
WHEN "00010000" => S_TRIG <= "00100000"; cnt <= 0;
WHEN "00100000" => S_TRIG <= "01000000"; cnt <= 0;
WHEN "01000000" => S_TRIG <= "10000000"; cnt <= 0;
WHEN "10000000" => S_TRIG <= "00000001"; cnt <= 0;
WHEN OTHERS => S_TRIG <= "00000001"; cnt <= 0;
END CASE;
WHEN trig =>
CASE S_TRIG IS
WHEN "00000001" => TRIG0 <= '1';
WHEN "00000010" => TRIG1 <= '1';
WHEN "00000100" => TRIG2 <= '1';
WHEN "00001000" => TRIG3 <= '1';
WHEN "00010000" => TRIG4 <= '1';
WHEN "00100000" => TRIG5 <= '1';
WHEN "01000000" => TRIG6 <= '1';
WHEN "10000000" => TRIG7 <= '1';
WHEN OTHERS => TRIG1 <= '1';
END CASE;
WHEN wfor => TRIG0 <= '0';
TRIG1 <= '0';
TRIG2 <= '0';
TRIG3 <= '0';
TRIG4 <= '0';
TRIG5 <= '0';
TRIG6 <= '0';
TRIG7 <= '0';
WHEN echo =>
IF CLK'EVENT AND CLK = '1' THEN cnt <= cnt + 1; 就这一行出现了标题中的错误
END IF;
WHEN outdis =>
CASE S_TRIG IS
WHEN "00000001" =>
IF cnt < 12 THEN DIS0 <= "00";
ELSIF cnt < 58 THEN DIS0 <= "01";
ELSIF cnt < 176 THEN DIS0 <= "10";
ELSE DIS0 <= "11";
END IF;
WHEN "00000010" =>
IF cnt < 12 THEN DIS1 <= "00";
ELSIF cnt < 58 THEN DIS1 <= "01";
ELSIF cnt < 176 THEN DIS1 <= "10";
ELSE DIS1 <= "11";
END IF;
WHEN "00000100" =>
IF cnt < 12 THEN DIS2 <= "00";
ELSIF cnt < 58 THEN DIS2 <= "01";
ELSIF cnt < 176 THEN DIS2 <= "10";
ELSE DIS2 <= "11";
END IF;
WHEN "00001000" =>
IF cnt < 12 THEN DIS3 <= "00";
ELSIF cnt < 58 THEN DIS3 <= "01";
ELSIF cnt < 176 THEN DIS3 <= "10";
ELSE DIS3 <= "11";
END IF;
WHEN "00010000" =>
IF cnt < 12 THEN DIS4 <= "00";
ELSIF cnt < 58 THEN DIS4 <= "01";
ELSIF cnt < 176 THEN DIS4 <= "10";
ELSE DIS4 <= "11";
END IF;
WHEN "00100000" =>
IF cnt < 12 THEN DIS5 <= "00";
ELSIF cnt < 58 THEN DIS5 <= "01";
ELSIF cnt < 176 THEN DIS5 <= "10";
ELSE DIS5 <= "11";
END IF;
WHEN "01000000" =>
IF cnt < 12 THEN DIS6 <= "00";
ELSIF cnt < 58 THEN DIS6 <= "01";
ELSIF cnt < 176 THEN DIS6 <= "10";
ELSE DIS6 <= "11";
END IF;
WHEN "10000000" =>
IF cnt < 12 THEN DIS7 <= "00";
ELSIF cnt < 58 THEN DIS7 <= "01";
ELSIF cnt < 176 THEN DIS7 <= "10";
ELSE DIS7 <= "11";
END IF;
WHEN OTHERS => NULL;
END CASE;
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
END behave;
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baowxz 2020-03-13
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所以怎么改的 方便呢额?
wingcmos 2016-08-25
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我感觉是因为cnt在不同case的不同分支中赋值出现了错误,但是不知道怎么修改
wingcmos 2016-08-25
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也就是说不能在case语句里判断时钟上升沿?
fly 100% 2016-08-25
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clk 是敏感信号不能再里面在判断clk的值了 可以再起一个独立的模块用clk posedge 做触发进行赋值

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