VHDL初学者,帮忙看看什么问题。
hit?? 2016-09-11 12:43:14 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADS8321 IS
PORT(dout:IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clk,cs: IN STD_LOGIC;
chu: OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END ENTITY ADS8321;
ARCHITECTURE behave OF ADS8321 IS
VARIABLE ci:INTEGER;
BEGIN
PROCESS(cs,clk)
BEGIN
IF(cs’EVENT AND cs=’0’)THEN
ci:=0;
ELSIF(cs='0')THEN
IF(clk’EVENT AND clk=’1’)THEN
ci:=ci+1;
IF(ci>6)THEN
chu<=dout;
END IF;
END IF;
ELSIF(cs'EVENT AND cs='1')THEN
ci:=0;
END IF;
END PROCESS;
END ARCHITECTURE behave;
报错:
Error (10500): VHDL syntax error at Vhdl1.vhd(17) near text
求大神帮我纠错。