verilog 中generate模块问题，求指点

[Wiley.Wen]

使用generate模块编码时，碰到一个问题，内部 s_rd_en中i变量必须保持相同系数，否则会报同一变量被多个驱动的问题。
按理说各个条件中都是互斥的，不存在同一变量同时被存在两个drive的问题，为什么还会报这个错误？
帮忙看看，原因是为什么？

代码如下：

localparam NUM_CE = 8;
localparam NUM_BLOCK = 80;
localparam NUM_BLOCK_k5_LOOP = 3*NUM_CE;
localparam NUM_BLOCK_k3_LOOP = 5*NUM_CE;

reg  [2:0]     s_mode_state[NUM_CE-1:0];
reg  [5:0]     s_rd_en [NUM_BLOCK-1:0];

genvar i;                                          
generate                                           
    for (i=0;i<NUM_CE;i=i+1)                       
    begin:TEST   ///          
        always @(posedge I_clk or negedge I_rst_n)
        begin
        	if(I_rst_n==1'b0)begin
              s_rd_en[0*NUM_CE+i]  <= 6'b0;      
              s_rd_en[1*NUM_CE+i]  <= 6'b0;     
              s_rd_en[2*NUM_CE+i]  <= 6'b0;      
              s_rd_en[3*NUM_CE+i]  <= 6'b0;     
              s_rd_en[4*NUM_CE+i]  <= 6'b0;     
              s_rd_en[5*NUM_CE+i]  <= 6'b0;
              s_rd_en[6*NUM_CE+i]  <= 6'b0;
              s_rd_en[7*NUM_CE+i]  <= 6'b0;
              s_rd_en[8*NUM_CE+i]  <= 6'b0;
              s_rd_en[9*NUM_CE+i]  <= 6'b0;           
        	end
    	    else begin
    	      case(s_mode_state[i])
    	          3'b001:begin
                    s_rd_en[0*NUM_CE+i]  <= (s_ram_batch_ren_cnt0[4*(i+1)-1:4*i]==4'd0) ? s_rd_ofmap_en0[6*(i+1)-1:6*i]:6'b0;                  
                    s_rd_en[1*NUM_CE+i]  <= (s_ram_batch_ren_cnt0[4*(i+1)-1:4*i]==4'd1) ? s_rd_ofmap_en0[6*(i+1)-1:6*i]:6'b0;                 
                    s_rd_en[2*NUM_CE+i]  <= (s_ram_batch_ren_cnt0[4*(i+1)-1:4*i]==4'd2) ? s_rd_ofmap_en0[6*(i+1)-1:6*i]:6'b0;                  
                    s_rd_en[3*NUM_CE+i]  <= (s_ram_batch_ren_cnt0[4*(i+1)-1:4*i]==4'd3) ? s_rd_ofmap_en0[6*(i+1)-1:6*i]:6'b0;                 
                    s_rd_en[4*NUM_CE+i]  <= (s_ram_batch_ren_cnt0[4*(i+1)-1:4*i]==4'd4) ? s_rd_ofmap_en0[6*(i+1)-1:6*i]:6'b0;                 
                    s_rd_en[5*NUM_CE+i]  <= (s_ram_batch_ren_cnt0[4*(i+1)-1:4*i]==4'd5) ? s_rd_ofmap_en0[6*(i+1)-1:6*i]:6'b0;     
    	          end
    	          3'b010:begin
                    s_rd_en[0*NUM_BLOCK_k5_LOOP+i*3+0]  <= (s_ram_batch_ren_cnt1[4*(i+1)-1:4*i]==4'd0) ? s_rd_ofmap_en0[6*(i+1)-1:6*i]:6'd0;
                    s_rd_en[0*NUM_BLOCK_k5_LOOP+i*3+1]  <= (s_ram_batch_ren_cnt1[4*(i+1)-1:4*i]==4'd0) ? s_rd_ofmap_en1[6*(i+1)-1:6*i]:6'd0;
                    s_rd_en[0*NUM_BLOCK_k5_LOOP+i*3+2]  <= (s_ram_batch_ren_cnt1[4*(i+1)-1:4*i]==4'd0) ? s_rd_ofmap_en2[6*(i+1)-1:6*i]:6'd0;
                    s_rd_en[1*NUM_BLOCK_k5_LOOP+i*3+0]  <= (s_ram_batch_ren_cnt1[4*(i+1)-1:4*i]==4'd1) ? s_rd_ofmap_en0[6*(i+1)-1:6*i]:6'd0;
                    s_rd_en[1*NUM_BLOCK_k5_LOOP+i*3+1]  <= (s_ram_batch_ren_cnt1[4*(i+1)-1:4*i]==4'd1) ? s_rd_ofmap_en1[6*(i+1)-1:6*i]:6'd0;               
                    s_rd_en[1*NUM_BLOCK_k5_LOOP+i*3+2]  <= (s_ram_batch_ren_cnt1[4*(i+1)-1:4*i]==4'd1) ? s_rd_ofmap_en2[6*(i+1)-1:6*i]:6'd0;
                    s_rd_en[2*NUM_BLOCK_k5_LOOP+i*3+0]  <= (s_ram_batch_ren_cnt1[4*(i+1)-1:4*i]==4'd2) ? s_rd_ofmap_en0[6*(i+1)-1:6*i]:6'd0;
                    s_rd_en[2*NUM_BLOCK_k5_LOOP+i*3+1]  <= (s_ram_batch_ren_cnt1[4*(i+1)-1:4*i]==4'd2) ? s_rd_ofmap_en1[6*(i+1)-1:6*i]:6'd0;
                    s_rd_en[2*NUM_BLOCK_k5_LOOP+i*3+2]  <= (s_ram_batch_ren_cnt1[4*(i+1)-1:4*i]==4'd2) ? s_rd_ofmap_en2[6*(i+1)-1:6*i]:6'd0;    
    	          end	  
    	          3'b100:begin
                    s_rd_en[0*NUM_BLOCK_k3_LOOP+i*5+0]  <= (s_ram_batch_ren_cnt25[4*(i+1)-1:4*i]==4'd0) ? s_rd_ofmap_en0[6*(i+1)-1:6*i]:6'd0;
                    s_rd_en[0*NUM_BLOCK_k3_LOOP+i*5+1]  <= (s_ram_batch_ren_cnt25[4*(i+1)-1:4*i]==4'd0) ? s_rd_ofmap_en1[6*(i+1)-1:6*i]:6'd0;
                    s_rd_en[0*NUM_BLOCK_k3_LOOP+i*5+2]  <= (s_ram_batch_ren_cnt25[4*(i+1)-1:4*i]==4'd0) ? s_rd_ofmap_en2[6*(i+1)-1:6*i]:6'd0;
                    s_rd_en[0*NUM_BLOCK_k3_LOOP+i*5+3]  <= (s_ram_batch_ren_cnt25[4*(i+1)-1:4*i]==4'd0) ? s_rd_ofmap_en3[6*(i+1)-1:6*i]:6'd0;
                    s_rd_en[0*NUM_BLOCK_k3_LOOP+i*5+4]  <= (s_ram_batch_ren_cnt25[4*(i+1)-1:4*i]==4'd0) ? s_rd_ofmap_en4[6*(i+1)-1:6*i]:6'd0;               
                    s_rd_en[1*NUM_BLOCK_k3_LOOP+i*5+0]  <= (s_ram_batch_ren_cnt25[4*(i+1)-1:4*i]==4'd1) ? s_rd_ofmap_en0[6*(i+1)-1:6*i]:6'd0;
                    s_rd_en[1*NUM_BLOCK_k3_LOOP+i*5+1]  <= (s_ram_batch_ren_cnt25[4*(i+1)-1:4*i]==4'd1) ? s_rd_ofmap_en1[6*(i+1)-1:6*i]:6'd0;
                    s_rd_en[1*NUM_BLOCK_k3_LOOP+i*5+2]  <= (s_ram_batch_ren_cnt25[4*(i+1)-1:4*i]==4'd1) ? s_rd_ofmap_en2[6*(i+1)-1:6*i]:6'd0;
                    s_rd_en[1*NUM_BLOCK_k3_LOOP+i*5+3]  <= (s_ram_batch_ren_cnt25[4*(i+1)-1:4*i]==4'd1) ? s_rd_ofmap_en3[6*(i+1)-1:6*i]:6'd0;
                    s_rd_en[1*NUM_BLOCK_k3_LOOP+i*5+4]  <= (s_ram_batch_ren_cnt25[4*(i+1)-1:4*i]==4'd1) ? s_rd_ofmap_en4[6*(i+1)-1:6*i]:6'd0;       
    	          end
    	          default:begin
                    s_rd_en[0*NUM_CE+i]  <= 6'b0;      
                    s_rd_en[1*NUM_CE+i]  <= 6'b0;     
                    s_rd_en[2*NUM_CE+i]  <= 6'b0;      
                    s_rd_en[3*NUM_CE+i]  <= 6'b0;     
                    s_rd_en[4*NUM_CE+i]  <= 6'b0;     
                    s_rd_en[5*NUM_CE+i]  <= 6'b0;
                    s_rd_en[6*NUM_CE+i]  <= 6'b0;
                    s_rd_en[7*NUM_CE+i]  <= 6'b0;
                    s_rd_en[8*NUM_CE+i]  <= 6'b0;
                    s_rd_en[9*NUM_CE+i]  <= 6'b0;    
    	          end
            
    	      endcase	      
    	    end
        
        end
    end
endgenerate    

[Wiley.Wen]

变量是否被重复赋值，不考虑条件，只考虑不同always模块下是否同时出现，语法知识不过硬！！！

[hsusea]

多个always程序块里不能对同一reg定义

[李锐博恩]

你只是截取了一部分程序贴出来，我猜你全部程序中肯定还有其他always 块，并且对出现问题的变量也赋值了。这是不能综合的