用Quartus II设计fir滤波器用modelsim仿真时出错

[A_Apple_Tree]

使用是Quartus II13.1，仿真用的modelsim 10.0d
想问一下在Quartus II中使用了FIR IP核，然后在仿真时出现了下面的错误应该怎么解决，另外为什么生成的fir的文件是
.vhd格式的，在生成IP核时选择了Verilog。

# ALTERA version supports only a single HDL
# ** Fatal: (vsim-3039) E:/Quartus_/qam_a/fir_filt.v(47): Instantiation of 'fir_IP' failed.
#    Time: 0 ps  Iteration: 0  Instance: /qam_a_vlg_tst/i1/fir_filtqam File: E:/Quartus_/qam_a/fir_filt.v
# FATAL ERROR while loading design
# Error loading design
# Error: Error loading design 
#        Pausing macro execution 
# MACRO ./qam_a_run_msim_rtl_verilog.do PAUSED at line 47

[worldy]

E:/Quartus_/qam_a/fir_filt.v 这个文件不存在？