ISE错误代码899

[LQL_01]

module test1(input wire [1:0]ST,
output reg [3:0]Q,
input CE,CR,CP
);
reg [3:0]x;
always@(posedge CP,negedge CR)
begin
case(ST)
2'b00:x=4'b0100;
2'b01:x=4'b0111;
2'b10:x=4'b1001;
default:x=4'b1011;
endcase
if(~CR)Q<=4'b0000;
else if(CE)
begin
if(Q>=x)
Q<=4'b0000;
else
Q<=Q+1'b1;
end
else
Q<=Q;
end
endmodule
错误提示：ERROR:Xst:899 - "test1.v" line 28: The logic for <x> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
请问该怎么解决呢

[我是Trustintruth]

把always块拆开写吧，不要写一个，敏感信号列表也改一下不要用逗号了。拆成两个之后敏感信号列表对应拆开。
感觉就是always块中顺序执行他无法达到

[李锐博恩]

case拿出去，放到另一个always 块中，你这程序写的让人看不出意图……仅供参考