求助！采用全并行方式设计设计FIR滤波器，求和后结果为0，请问是什么问题？

[axiongxida]

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

entity FIRParallel is
port(
rst:in std_logic;
clk:in std_logic;
Xin:in std_logic_vector(11 downto 0);
Yout:out std_logic_vector(28 downto 0)
);
end FIRParallel;

architecture arch_FIRParallel of FIRParallel is
component mult
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(24 DOWNTO 0)
);
end component;

component AddSub
port(
a : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
clk : IN STD_LOGIC;
s : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
);
end component;

component filter_adder
port(
a : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(24 DOWNTO 0);
clk : IN STD_LOGIC;
s : OUT STD_LOGIC_VECTOR(28 DOWNTO 0)
);
end component;

type add_res is array(7 downto 0) of std_logic_vector(12 downto 0);
signal add_reg:add_res;

type mult_regs is array(7 downto 0) of std_logic_vector(24 downto 0);
signal mult_reg:mult_regs;

type xin_regs is array(15 downto 0) of std_logic_vector(11 downto 0);
signal xin_reg:xin_regs;

signal sum0:std_logic_vector(28 downto 0):=(others=>'0');
signal sum1:std_logic_vector(28 downto 0);
signal sum2:std_logic_vector(28 downto 0);
signal sum3:std_logic_vector(28 downto 0);
signal sum4:std_logic_vector(28 downto 0);
signal sum5:std_logic_vector(28 downto 0);
signal sum6:std_logic_vector(28 downto 0);
signal sum7:std_logic_vector(28 downto 0);
signal sum8:std_logic_vector(28 downto 0);

--Coeffections
constant co0:std_logic_vector(11 downto 0):= X"000";
constant co1:std_logic_vector(11 downto 0):= X"FFD";
constant co2:std_logic_vector(11 downto 0):= X"00F";
constant co3:std_logic_vector(11 downto 0):= X"02E";
constant co4:std_logic_vector(11 downto 0):= X"F8B";
constant co5:std_logic_vector(11 downto 0):= X"EF9";
constant co6:std_logic_vector(11 downto 0):= X"24E";
constant co7:std_logic_vector(11 downto 0):= X"7FF";

begin
adder0:AddSub port map (
a => xin_reg(0),
b => xin_reg(15),
clk => clk,
s => add_reg(0));

adder1:AddSub port map (
a => xin_reg(1),
b => xin_reg(14),
clk => clk,
s => add_reg(1));

adder2:AddSub port map (
a => xin_reg(2),
b => xin_reg(13),
clk => clk,
s => add_reg(2));

adder3:AddSub port map (
a => xin_reg(3),
b => xin_reg(12),
clk => clk,
s => add_reg(3));

adder4:AddSub port map (
a => xin_reg(4),
b => xin_reg(11),
clk => clk,
s => add_reg(4));

adder5:AddSub port map (
a => xin_reg(5),
b => xin_reg(10),
clk => clk,
s => add_reg(5));

adder6:AddSub port map (
a => xin_reg(6),
b => xin_reg(9),
clk => clk,
s => add_reg(6));

adder7:AddSub port map (
a => xin_reg(7),
b => xin_reg(8),
clk => clk,
s => add_reg(7));

mult_u0:mult port map (
clk=>clk,
a=>co0,
b=>add_reg(0),
p=>mult_reg(0));

mult_u1:mult port map (
clk=>clk,
a=>co1,
b=>add_reg(1),
p=>mult_reg(1));

mult_u2:mult port map (
clk=>clk,
a=>co2,
b=>add_reg(2),
p=>mult_reg(2));

mult_u3:mult port map (
clk=>clk,
a=>co3,
b=>add_reg(3),
p=>mult_reg(3));

mult_u4:mult port map (
clk=>clk,
a=>co4,
b=>add_reg(4),
p=>mult_reg(4));

mult_u5:mult port map (
clk=>clk,
a=>co5,
b=>add_reg(5),
p=>mult_reg(5));

mult_u6:mult port map (
clk=>clk,
a=>co6,
b=>add_reg(6),
p=>mult_reg(6));

mult_u7:mult port map (
clk=>clk,
a=>co7,
b=>add_reg(7),
p=>mult_reg(7));

filter_adder_u0:filter_adder port map (
a => sum0,
b => mult_reg(0),
clk => clk,
s => sum1);

filter_adder_u1:filter_adder port map (
a => sum1,
b => mult_reg(1),
clk => clk,
s => sum2);

filter_adder_u2:filter_adder port map (
a => sum2,
b => mult_reg(2),
clk => clk,
s => sum3);

filter_adder_u3:filter_adder port map (
a => sum3,
b => mult_reg(3),
clk => clk,
s => sum4);

filter_adder_u4:filter_adder port map (
a => sum4,
b => mult_reg(4),
clk => clk,
s => sum5);

filter_adder_u5:filter_adder port map (
a => sum5,
b => mult_reg(5),
clk => clk,
s => sum6);

filter_adder_u6:filter_adder port map (
a => sum6,
b => mult_reg(6),
clk => clk,
s => sum7);

filter_adder_u7:filter_adder port map (
a => sum7,
b => mult_reg(7),
clk => clk,
s => sum8);

Yout <= sum8;

PXin:process(rst,clk)
begin
if rst = '1' then
for i in 0 to 15 loop
xin_reg(i) <= (others=>'0');
end loop;
elsif rising_edge(clk) then
for i in 0 to 14 loop
xin_reg(i+1) <= xin_reg(i);
end loop;
xin_reg(0) <= Xin;
end if;
end process PXin;
end arch_FIRParallel;