QUARTUS II 总是提示错误代码10170 求求大神啊

2018-06-27 10:29:09 5.1k 阅读 AI 写同款 · GEO 优化AI 选题数据监测一键分发 ›

Quartus 18.1下载配置全攻略：从编译到烧录的完整流程（附常见错误解决）本文详细介绍了Quartus 18.1从环境搭建到程序烧录的完整开发流程，包括安装配置、工程创建、编译优化及常见错误解决方案。特别针对FPGA开发者提供了实用的下载设置技巧和性能优化策略，帮助提升开发效率并避免常见陷阱。阅读详情

module register(opc_iraddr,data,ena,clk1,rst);
output [15:0] opc_iraddr;
input [7:0] data;
input ena, clk1, rst;
reg [15:0] opc_iraddr;
reg state;

always @(posedge clk1)
begin
if(rst)
begin
opc_iraddr<=16'b0000_0000_0000_0000;
state<=1'b0;
end
else
begin
if(ena) //如果加载指令寄存器信号load_ir到来，
begin //分两个时钟每次8位加载指令寄存器
casex(state) //先高字节，后低字节
1’b0: begin
opc_iraddr[15:8]<=data;
state<=1;
end
1’b1: begin
opc_iraddr[7:0]<=data;
state<=0;
end
default: begin
opc_iraddr[15:0]<=16'bxxxxxxxxxxxxxxxx;
state<=1'bx;
end
endcase
end
else
state<=1'b0;
end
end
endmodule

错误：
Error (10170): Verilog HDL syntax error at register.v(20) near text ?
Error (10170): Verilog HDL syntax error at register.v(20) near text "?; expecting ":", or ","
Error (10170): Verilog HDL syntax error at register.v(20) near text ?
Error (10170): Verilog HDL syntax error at register.v(24) near text ?
Error (10170): Verilog HDL syntax error at register.v(24) near text "?; expecting ":", or ","
Error (10170): Verilog HDL syntax error at register.v(24) near text ?
Error (10112): Ignored design unit "register" at register.v(1) due to previous errors
Info: Found 0 design units, including 0 entities, in source file register.v
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 7 errors, 0 warnings
Error: Peak virtual memory: 318 megabytes
Error: Processing ended: Wed Jun 27 22:20:52 2018
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 9 errors, 0 warnings

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