vhdl语言同一个结构体中进程和元件调用不能共存吗？

qq_28337303 2018-08-23 04:14:51

本人新手小白，关于元件调用和进程的问题一直没弄明白，程序大概是计数器计数延时5ms，然后读取一次外部开关的状态，读取前调用一个按键延时去抖动程序，然后怎么编译都不通过，附上代码和错误号：Error (10500): VHDL syntax error at clk_5ms.vhd(52) near text "component"; expecting "end", or "(", or an identifier ("component" is a reserved keyword), or a concurrent statement

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

use ieee.numeric_std.all;



entity clk_5ms is

port(

	i_clk : in std_logic; --时钟

	reset: in std_logic; --复位信号

	i_x1 : in std_logic; 

	i_x10 : in std_logic; 

	i_x100: in std_logic;

	dir_in2: in std_logic; 

	data_in2: in std_logic_vector(7 downto 0);

	data_out2: inout std_logic_vector( 7 downto 0 ); 

	dir_out2: out std_logic;

	b_out:out std_logic_vector(7 downto 0);

	start2:out std_logic

	);

end entity;



architecture rtl of encode_hw is

signal x1_rdy,x10_rdy,x100_rdy :std_logic;

signal counter:std_logic_vector(19 downto 0);



begin

process(i_clk,reset)

begin

	if(reset='0')then

		data_out2<="00000000";

		counter<="00000000000000000000";

		b_out<="00000000";

	else

		if(counter="10011000100101101000")then

			data_out2<=data_in2; dir_out2<=dir_in2; start2<='0'; counter<="00000000000000000000";

		else

			data_out2<="00000000"; dir_out2<=dir_out2; start2<='1'; counter<=counter+1;

		end if;

		

		if(x1_rdy='1')and(x10_rdy='0')and(x100_rdy='0')then

			b_out<="0000_0001";

		elsif(x1_rdy='0')and(x10_rdy='1')and(x100_rdy='0')then

			b_out<="0000_1010";

		elsif(x1_rdy='0')and(x10_rdy='0')and(x100_rdy='1')then

			b_out<="0110_0100";

		else null;

		end if;

	end if;

end process;



component key_gen_hw is

port(		clk:in std_logic;

			key1:in std_logic;

			key2:in std_logic;

			key3:in std_logic;

			key1_rdy:out std_logic;

			key2_rdy:out std_logic;

			key3_rdy:out std_logic

			);

end component;

begin

uo:key_gen_hw port map(clk=>i_clk,key1=>i_x1,key2=>i_x10,key3=>i_x100,key1_rdy=>x1_rdy,key2_rdy=>x10_rdy,key3_rdy=>x100_rdy);

end;