ADC-Measurement-1222-2004下载

PIPI_333 2018-09-01 02:39:33

该文档介绍了ADC的使用方法，以及adc输入滤波电阻电容参数的选择
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该文档介绍了ADC的使用方法，以及adc输入滤波电阻电容参数的选择

pipeline ADC simulink

详细分析ADC的输入噪声问题和解决方案。 In this discussion we have considered the input-referred noise, common to all ADCs. In precision, low-frequency measurement applications, effects of this noise can be reduced by digitally averaging the ADC output data, using lower sampling rates and additional hardware. While the resolution of the ADC can actually be increased by this averaging process, integral-nonlinearity errors are not reduced. Only a small amount of input-referred noise is needed to increase the resolution by the averaging technique; however, use of increased noise requires a larger number of samples in the average, so a point of diminishing returns is reached.

This dissertation proposes three circuit design techniques for successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the proof-of-concept prototypes, the proposed techniques are able to improve the operating speed and achieve excellent energy efficiency. The proposed techniques and chip measurement results are sketched as follows: The first technique is a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total sampling capacitance are reduced by about 81.3% and 50%, respectively. A 10-bit, 50-MS/s SAR ADC with the proposed monotonic capacitor switching procedure is implemented in a 0.13-μm 1P8M CMOS technology. The prototype ADC consumes 0.92 mW from a 1.2-V supply, and the effective number of bit (ENOB) is 8.48 bits. The resulting figure of merit (FOM) is 52 fJ/conversion-step. However, the signal-dependent offset caused by the variation of the input common-mode voltage degrades the linearity of ADC. We proposed an improved comparator design to avoid the linearity degradation. Besides, to avoid a clock signal with frequency higher than sampling rate, we used an asynchronous control circuit to internally generate the necessary control signals. The revised prototype is also implemented in a 0.13-μm 1P8M CMOS technology. It consumes 0.826 mW from a 1.2-V supply and achieves an ENOB of 9.18 bits. The resultant FOM is 29 fJ/conversion-step.

5G/ADC/BIOA transistor level implementation of a 3 bit digital harmonic canceling (DHC) digital to analog converter (DAC), and a 10 bit successive approximation register (SAR) analog to digital converter (ADC) is designed. The circuits are intended to be a part of a bio-impedance measurement system in which a current is injected into the myocardium tissue and blood pool for the purpose of determining the heart’s stroke volume. The DHC DAC injects a 100 µArms current at a 20 kHz fundamental frequency using appropriately weighted current mirrors from a 160 kHz square-wave reference clock. A fs = 160 kS/s ADC is designed with synchronous SAR logic, bottom-plate sampling, and a charge-redistribution capacitive DAC.

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